[PATCH] D45995: [DAGCombiner] Set the right SDLoc on a newly-created zextload (1/N)

[Adrian Prantl via Phabricator via llvm-commits]

aprantl added a comment.

So if I understand correctly the new instruction ordering in the assembler output is actually closer to the instruction ordering in the IR, since we are now setting the order metadata correctly in DAGCombine?


https://reviews.llvm.org/D45995