[PATCH] D46101: [PowerPC] vectorize Sum of Absolute Difference

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added a reviewer: RKSimon.
RKSimon added inline comments.


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Comment at: lib/CodeGen/SelectionDAG/TargetLowering.cpp:4362
+// 6:    %7 = select <N x i1> %5, <N x i32> %4, <N x i32> %6
+// This is useful as it is the input into a SAD pattern.
+bool
----------------
In a more general setting we probably need to support ABS(SUB(ZEXT(x)), ZEXT(y))) as well


================
Comment at: lib/Target/PowerPC/PPCISelLowering.cpp:12110
+  // feeding them into several SADs, and then reducing over those.
+  if (VT.getVectorNumElements() != 16 && VT.getVectorNumElements() != 8)
+    return SDValue();
----------------
This (and the comment) needs updating for PPC, maybe merge the 2 ifs to just:
```
if (VT != MVT::v16i8 && VT != MVT::v8i16)
  return SDValue();
```


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Comment at: lib/Target/PowerPC/PPCISelLowering.cpp:12130
+      MinNode = DAG.getMachineNode(PPC::VMINSB, DL, MVT::v16i8,
+                                   Zext0.getOperand(0), Zext1.getOperand(0));
+    }
----------------
How come PPC doesn't use the ISD::SMAX/SMIN/UMAX/UMIN opcodes? It'd remove a lot of this duplication.


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Comment at: test/CodeGen/PowerPC/ppc64_basicSAD.ll:1
+; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -verify-machineinstrs | FileCheck %s
+
----------------
Why not use utils/update_llc_test_checks.py ?


https://reviews.llvm.org/D46101