[llvm] r331084 - [X86] Merge some x87 instruction instregex single matches. NFCI.
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Fri Apr 27 14:14:19 PDT 2018
Author: rksimon
Date: Fri Apr 27 14:14:19 2018
New Revision: 331084
URL: http://llvm.org/viewvc/llvm-project?rev=331084&view=rev
Log:
[X86] Merge some x87 instruction instregex single matches. NFCI.
Modified:
llvm/trunk/lib/Target/X86/X86SchedBroadwell.td
llvm/trunk/lib/Target/X86/X86SchedHaswell.td
llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td
llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td
llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td
llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td
Modified: llvm/trunk/lib/Target/X86/X86SchedBroadwell.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedBroadwell.td?rev=331084&r1=331083&r2=331084&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedBroadwell.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedBroadwell.td Fri Apr 27 14:14:19 2018
@@ -472,9 +472,7 @@ def: InstRW<[BWWriteResGroup10], (instre
"MMX_MOVQ64mr",
"MOVNTI_64mr",
"MOVNTImr",
- "ST_FP32m",
- "ST_FP64m",
- "ST_FP80m",
+ "ST_FP(32|64|80)m",
"VEXTRACTF128mr",
"VEXTRACTI128mr",
"(V?)MOVAPD(Y?)mr",
@@ -810,14 +808,8 @@ def BWWriteResGroup44 : SchedWriteRes<[B
let NumMicroOps = 3;
let ResourceCycles = [1,1,1];
}
-def: InstRW<[BWWriteResGroup44], (instregex "ISTT_FP16m",
- "ISTT_FP32m",
- "ISTT_FP64m",
- "IST_F16m",
- "IST_F32m",
- "IST_FP16m",
- "IST_FP32m",
- "IST_FP64m")>;
+def: InstRW<[BWWriteResGroup44], (instregex "IST(T?)_FP(16|32|64)m",
+ "IST_F(16|32)m")>;
def BWWriteResGroup45 : SchedWriteRes<[BWPort0156]> {
let Latency = 4;
@@ -921,9 +913,7 @@ def BWWriteResGroup58 : SchedWriteRes<[B
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[BWWriteResGroup58], (instregex "LD_F32m",
- "LD_F64m",
- "LD_F80m",
+def: InstRW<[BWWriteResGroup58], (instregex "LD_F(32|64|80)m",
"VBROADCASTF128",
"VBROADCASTI128",
"VBROADCASTSDYrm",
@@ -1392,15 +1382,8 @@ def BWWriteResGroup101 : SchedWriteRes<[
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[BWWriteResGroup101], (instregex "ADD_F32m",
- "ADD_F64m",
- "ILD_F16m",
- "ILD_F32m",
- "ILD_F64m",
- "SUBR_F32m",
- "SUBR_F64m",
- "SUB_F32m",
- "SUB_F64m",
+def: InstRW<[BWWriteResGroup101], (instregex "(ADD|SUB|SUBR)_F(32|64)m",
+ "ILD_F(16|32|64)m",
"VADDPDYrm",
"VADDPSYrm",
"VADDSUBPDYrm",
@@ -1593,8 +1576,7 @@ def BWWriteResGroup123 : SchedWriteRes<[
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[BWWriteResGroup123], (instregex "MUL_F32m",
- "MUL_F64m",
+def: InstRW<[BWWriteResGroup123], (instregex "MUL_F(32|64)m",
"VPCMPGTQYrm",
"VPMADDUBSWYrm",
"VPMADDWDYrm",
@@ -1667,12 +1649,7 @@ def BWWriteResGroup135 : SchedWriteRes<[
let NumMicroOps = 3;
let ResourceCycles = [2,1];
}
-def: InstRW<[BWWriteResGroup135], (instregex "ADD_FI16m",
- "ADD_FI32m",
- "SUBR_FI16m",
- "SUBR_FI32m",
- "SUB_FI16m",
- "SUB_FI32m",
+def: InstRW<[BWWriteResGroup135], (instregex "(ADD|SUB|SUBR)_FI(16|32)m",
"VROUNDPDYm",
"VROUNDPSYm")>;
@@ -1716,8 +1693,7 @@ def BWWriteResGroup141 : SchedWriteRes<[
let NumMicroOps = 3;
let ResourceCycles = [1,1,1];
}
-def: InstRW<[BWWriteResGroup141], (instregex "MUL_FI16m",
- "MUL_FI32m")>;
+def: InstRW<[BWWriteResGroup141], (instregex "MUL_FI(16|32)m")>;
def BWWriteResGroup142 : SchedWriteRes<[BWPort0,BWPort1,BWPort5]> {
let Latency = 14;
@@ -1894,8 +1870,7 @@ def BWWriteResGroup169 : SchedWriteRes<[
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[BWWriteResGroup169], (instregex "DIV_F32m",
- "DIV_F64m")>;
+def: InstRW<[BWWriteResGroup169], (instregex "DIV_F(32|64)m")>;
def BWWriteResGroup170 : SchedWriteRes<[BWPort0,BWPort015,BWFPDivider]> {
let Latency = 21;
@@ -1944,8 +1919,7 @@ def BWWriteResGroup177 : SchedWriteRes<[
let NumMicroOps = 3;
let ResourceCycles = [1,1,1];
}
-def: InstRW<[BWWriteResGroup177], (instregex "DIV_FI16m",
- "DIV_FI32m")>;
+def: InstRW<[BWWriteResGroup177], (instregex "DIV_FI(16|32)m")>;
def BWWriteResGroup179 : SchedWriteRes<[BWPort0,BWPort23,BWFPDivider]> {
let Latency = 21;
@@ -1960,8 +1934,7 @@ def BWWriteResGroup180 : SchedWriteRes<[
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[BWWriteResGroup180], (instregex "DIVR_F32m",
- "DIVR_F64m")>;
+def: InstRW<[BWWriteResGroup180], (instregex "DIVR_F(32|64)m")>;
def BWWriteResGroup181 : SchedWriteRes<[BWPort0,BWPort23,BWPort015,BWFPDivider]> {
let Latency = 27;
@@ -1975,8 +1948,7 @@ def BWWriteResGroup182 : SchedWriteRes<[
let NumMicroOps = 3;
let ResourceCycles = [1,1,1];
}
-def: InstRW<[BWWriteResGroup182], (instregex "DIVR_FI16m",
- "DIVR_FI32m")>;
+def: InstRW<[BWWriteResGroup182], (instregex "DIVR_FI(16|32)m")>;
def BWWriteResGroup183 : SchedWriteRes<[BWPort0,BWPort23,BWPort015,BWFPDivider]> {
let Latency = 29;
Modified: llvm/trunk/lib/Target/X86/X86SchedHaswell.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedHaswell.td?rev=331084&r1=331083&r2=331084&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedHaswell.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedHaswell.td Fri Apr 27 14:14:19 2018
@@ -539,8 +539,7 @@ def : InstRW<[HWWrite2P01], (instregex "
// FCOMI(P) FUCOMI(P).
// m.
-def : InstRW<[HWWrite3P01], (instregex "COM_FIr", "COM_FIPr", "UCOM_FIr",
- "UCOM_FIPr")>;
+def : InstRW<[HWWrite3P01], (instrs COM_FIPr, COM_FIr, UCOM_FIPr, UCOM_FIr)>;
// FTST.
def : InstRW<[HWWriteP1], (instregex "TST_F")>;
@@ -625,9 +624,7 @@ def HWWriteResGroup0_1 : SchedWriteRes<[
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[HWWriteResGroup0_1], (instregex "LD_F32m",
- "LD_F64m",
- "LD_F80m",
+def: InstRW<[HWWriteResGroup0_1], (instregex "LD_F(32|64|80)m",
"VBROADCASTF128",
"VBROADCASTI128",
"VBROADCASTSDYrm",
@@ -670,9 +667,7 @@ def: InstRW<[HWWriteResGroup1], (instreg
"MMX_MOVQ64mr",
"MOVNTI_64mr",
"MOVNTImr",
- "ST_FP32m",
- "ST_FP64m",
- "ST_FP80m",
+ "ST_FP(32|64|80)m",
"VEXTRACTF128mr",
"VEXTRACTI128mr",
"(V?)MOVAPD(Y?)mr",
@@ -1429,15 +1424,8 @@ def HWWriteResGroup52_1 : SchedWriteRes<
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[HWWriteResGroup52_1], (instregex "ADD_F32m",
- "ADD_F64m",
- "ILD_F16m",
- "ILD_F32m",
- "ILD_F64m",
- "SUBR_F32m",
- "SUBR_F64m",
- "SUB_F32m",
- "SUB_F64m",
+def: InstRW<[HWWriteResGroup52_1], (instregex "(ADD|SUB|SUBR)_F(32|64)m",
+ "ILD_F(16|32|64)m",
"VADDPDYrm",
"VADDPSYrm",
"VADDSUBPDYrm",
@@ -1549,14 +1537,8 @@ def HWWriteResGroup62 : SchedWriteRes<[H
let NumMicroOps = 3;
let ResourceCycles = [1,1,1];
}
-def: InstRW<[HWWriteResGroup62], (instregex "ISTT_FP16m",
- "ISTT_FP32m",
- "ISTT_FP64m",
- "IST_F16m",
- "IST_F32m",
- "IST_FP16m",
- "IST_FP32m",
- "IST_FP64m")>;
+def: InstRW<[HWWriteResGroup62], (instregex "IST(T?)_FP(16|32|64)m",
+ "IST_F(16|32)m")>;
def HWWriteResGroup63 : SchedWriteRes<[HWPort0,HWPort5,HWPort23]> {
let Latency = 10;
@@ -1896,18 +1878,17 @@ def HWWriteResGroup91_3 : SchedWriteRes<
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[HWWriteResGroup91_3], (instregex "MUL_F32m",
- "MUL_F64m",
- "VPCMPGTQYrm",
- "VPMADDUBSWYrm",
- "VPMADDWDYrm",
- "VPMULDQYrm",
- "VPMULHRSWYrm",
- "VPMULHUWYrm",
- "VPMULHWYrm",
- "VPMULLWYrm",
- "VPMULUDQYrm",
- "VPSADBWYrm")>;
+def: InstRW<[HWWriteResGroup91_3], (instregex "MUL_F(32|64)m",
+ "VPCMPGTQYrm",
+ "VPMADDUBSWYrm",
+ "VPMADDWDYrm",
+ "VPMULDQYrm",
+ "VPMULHRSWYrm",
+ "VPMULHUWYrm",
+ "VPMULHWYrm",
+ "VPMULLWYrm",
+ "VPMULUDQYrm",
+ "VPSADBWYrm")>;
def HWWriteResGroup92 : SchedWriteRes<[HWPort01,HWPort23]> {
let Latency = 11;
@@ -2005,12 +1986,7 @@ def HWWriteResGroup103 : SchedWriteRes<[
let NumMicroOps = 3;
let ResourceCycles = [2,1];
}
-def: InstRW<[HWWriteResGroup103], (instregex "ADD_FI16m",
- "ADD_FI32m",
- "SUBR_FI16m",
- "SUBR_FI32m",
- "SUB_FI16m",
- "SUB_FI32m",
+def: InstRW<[HWWriteResGroup103], (instregex "(ADD|SUB|SUBR)_FI(16|32)m",
"VROUNDPDYm",
"VROUNDPSYm")>;
@@ -2087,8 +2063,7 @@ def HWWriteResGroup115 : SchedWriteRes<[
let NumMicroOps = 3;
let ResourceCycles = [1,1,1];
}
-def: InstRW<[HWWriteResGroup115], (instregex "MUL_FI16m",
- "MUL_FI32m")>;
+def: InstRW<[HWWriteResGroup115], (instregex "MUL_FI(16|32)m")>;
def HWWriteResGroup116 : SchedWriteRes<[HWPort0,HWPort1,HWPort5]> {
let Latency = 9;
@@ -2300,8 +2275,7 @@ def HWWriteResGroup155 : SchedWriteRes<[
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[HWWriteResGroup155], (instregex "DIVR_F32m",
- "DIVR_F64m")>;
+def: InstRW<[HWWriteResGroup155], (instregex "DIVR_F(32|64)m")>;
def HWWriteResGroup155_1 : SchedWriteRes<[HWPort0,HWPort23,HWFPDivider]> {
let Latency = 26;
@@ -2367,8 +2341,7 @@ def HWWriteResGroup161 : SchedWriteRes<[
let NumMicroOps = 3;
let ResourceCycles = [1,1,1];
}
-def: InstRW<[HWWriteResGroup161], (instregex "DIVR_FI16m",
- "DIVR_FI32m")>;
+def: InstRW<[HWWriteResGroup161], (instregex "DIVR_FI(16|32)m")>;
def HWWriteResGroup162 : SchedWriteRes<[HWPort0]> {
let Latency = 24;
@@ -2384,8 +2357,7 @@ def HWWriteResGroup163 : SchedWriteRes<[
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[HWWriteResGroup163], (instregex "DIV_F32m",
- "DIV_F64m")>;
+def: InstRW<[HWWriteResGroup163], (instregex "DIV_F(32|64)m")>;
def HWWriteResGroup164 : SchedWriteRes<[HWPort4,HWPort6,HWPort23,HWPort237,HWPort0156]> {
let Latency = 30;
@@ -2406,8 +2378,7 @@ def HWWriteResGroup166 : SchedWriteRes<[
let NumMicroOps = 3;
let ResourceCycles = [1,1,1];
}
-def: InstRW<[HWWriteResGroup166], (instregex "DIV_FI16m",
- "DIV_FI32m")>;
+def: InstRW<[HWWriteResGroup166], (instregex "DIV_FI(16|32)m")>;
def HWWriteResGroup170 : SchedWriteRes<[HWPort5,HWPort6,HWPort23,HWPort06,HWPort0156]> {
let Latency = 35;
Modified: llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td?rev=331084&r1=331083&r2=331084&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td Fri Apr 27 14:14:19 2018
@@ -661,10 +661,7 @@ def SBWriteResGroup26_2 : SchedWriteRes<
let NumMicroOps = 3;
let ResourceCycles = [1,1,1];
}
-def: InstRW<[SBWriteResGroup26_2], (instregex "COM_FIPr",
- "COM_FIr",
- "UCOM_FIPr",
- "UCOM_FIr")>;
+def: InstRW<[SBWriteResGroup26_2], (instrs COM_FIPr, COM_FIr, UCOM_FIPr, UCOM_FIr)>;
def SBWriteResGroup27 : SchedWriteRes<[SBPort0,SBPort1]> {
let Latency = 4;
@@ -779,9 +776,7 @@ def SBWriteResGroup35_2 : SchedWriteRes<
let NumMicroOps = 3;
let ResourceCycles = [1,1,1];
}
-def: InstRW<[SBWriteResGroup35_2], (instregex "ISTT_FP16m",
- "ISTT_FP32m",
- "ISTT_FP64m",
+def: InstRW<[SBWriteResGroup35_2], (instregex "ISTT_FP(16|32|64)m",
"PUSHGS64")>;
def SBWriteResGroup36 : SchedWriteRes<[SBPort4,SBPort5,SBPort23]> {
@@ -910,11 +905,8 @@ def SBWriteResGroup53 : SchedWriteRes<[S
let NumMicroOps = 3;
let ResourceCycles = [1,2];
}
-def: InstRW<[SBWriteResGroup53], (instregex "ST_F32m",
- "ST_F64m",
- "ST_FP32m",
- "ST_FP64m",
- "ST_FP80m")>;
+def: InstRW<[SBWriteResGroup53], (instregex "ST_F(32|64)m",
+ "ST_FP(32|64|80)m")>;
def SBWriteResGroup54 : SchedWriteRes<[SBPort23]> {
let Latency = 7;
@@ -1394,20 +1386,15 @@ def SBWriteResGroup95 : SchedWriteRes<[S
let NumMicroOps = 3;
let ResourceCycles = [1,1,1];
}
-def: InstRW<[SBWriteResGroup95], (instregex "LD_F32m",
- "LD_F64m",
- "LD_F80m")>;
+def: InstRW<[SBWriteResGroup95], (instregex "LD_F(32|64|80)m")>;
def SBWriteResGroup97 : SchedWriteRes<[SBPort1,SBPort4,SBPort23]> {
let Latency = 9;
let NumMicroOps = 4;
let ResourceCycles = [1,1,2];
}
-def: InstRW<[SBWriteResGroup97], (instregex "IST_F16m",
- "IST_F32m",
- "IST_FP16m",
- "IST_FP32m",
- "IST_FP64m")>;
+def: InstRW<[SBWriteResGroup97], (instregex "IST_F(16|32)m",
+ "IST_FP(16|32|64)m")>;
def SBWriteResGroup97_2 : SchedWriteRes<[SBPort4,SBPort23,SBPort05]> {
let Latency = 9;
@@ -1451,15 +1438,8 @@ def SBWriteResGroup101 : SchedWriteRes<[
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SBWriteResGroup101], (instregex "ADD_F32m",
- "ADD_F64m",
- "ILD_F16m",
- "ILD_F32m",
- "ILD_F64m",
- "SUBR_F32m",
- "SUBR_F64m",
- "SUB_F32m",
- "SUB_F64m",
+def: InstRW<[SBWriteResGroup101], (instregex "(ADD|SUB|SUBR)_F(32|64)m",
+ "ILD_F(16|32|64)m",
"VADDPDYrm",
"VADDPSYrm",
"VADDSUBPDYrm",
@@ -1547,8 +1527,7 @@ def SBWriteResGroup111 : SchedWriteRes<[
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SBWriteResGroup111], (instregex "MUL_F32m",
- "MUL_F64m",
+def: InstRW<[SBWriteResGroup111], (instregex "MUL_F(32|64)m",
"VMULPDYrm",
"VMULPSYrm")>;
@@ -1564,13 +1543,7 @@ def SBWriteResGroup114 : SchedWriteRes<[
let NumMicroOps = 3;
let ResourceCycles = [2,1];
}
-def: InstRW<[SBWriteResGroup114], (instregex "ADD_FI16m",
- "ADD_FI32m",
- "SUBR_FI16m",
- "SUBR_FI32m",
- "SUB_FI16m",
- "SUB_FI32m")>;
-
+def: InstRW<[SBWriteResGroup114], (instregex "(ADD|SUB|SUBR)_FI(16|32)m")>;
def SBWriteResGroup116 : SchedWriteRes<[SBPort0,SBFPDivider]> {
let Latency = 14;
let NumMicroOps = 1;
@@ -1594,8 +1567,7 @@ def SBWriteResGroup119 : SchedWriteRes<[
let NumMicroOps = 3;
let ResourceCycles = [1,1,1];
}
-def: InstRW<[SBWriteResGroup119], (instregex "MUL_FI16m",
- "MUL_FI32m")>;
+def: InstRW<[SBWriteResGroup119], (instregex "MUL_FI(16|32)m")>;
def SBWriteResGroup120 : SchedWriteRes<[SBPort0,SBPort1,SBPort5,SBPort23]> {
let Latency = 15;
@@ -1673,20 +1645,14 @@ def SBWriteResGroup130 : SchedWriteRes<[
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SBWriteResGroup130], (instregex "DIVR_F32m",
- "DIVR_F64m",
- "DIV_F32m",
- "DIV_F64m")>;
+def: InstRW<[SBWriteResGroup130], (instregex "DIV(R?)_F(32|64)m")>;
def SBWriteResGroup131 : SchedWriteRes<[SBPort0,SBPort1,SBPort23]> {
let Latency = 34;
let NumMicroOps = 3;
let ResourceCycles = [1,1,1];
}
-def: InstRW<[SBWriteResGroup131], (instregex "DIVR_FI16m",
- "DIVR_FI32m",
- "DIV_FI16m",
- "DIV_FI32m")>;
+def: InstRW<[SBWriteResGroup131], (instregex "DIV(R?)_FI(16|32)m")>;
def SBWriteResGroup132 : SchedWriteRes<[SBPort0,SBPort23,SBPort05,SBFPDivider]> {
let Latency = 36;
Modified: llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td?rev=331084&r1=331083&r2=331084&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td Fri Apr 27 14:14:19 2018
@@ -563,9 +563,7 @@ def: InstRW<[SKLWriteResGroup11], (instr
"MMX_MOVQ64mr",
"MOVNTI_64mr",
"MOVNTImr",
- "ST_FP32m",
- "ST_FP64m",
- "ST_FP80m",
+ "ST_FP(32|64|80)m",
"VEXTRACTF128mr",
"VEXTRACTI128mr",
"(V?)MOVAPDYmr",
@@ -746,15 +744,9 @@ def SKLWriteResGroup30 : SchedWriteRes<[
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[SKLWriteResGroup30], (instregex "ADD_FPrST0",
- "ADD_FST0r",
- "ADD_FrST0",
- "SUBR_FPrST0",
- "SUBR_FST0r",
- "SUBR_FrST0",
- "SUB_FPrST0",
- "SUB_FST0r",
- "SUB_FrST0",
+def: InstRW<[SKLWriteResGroup30], (instregex "(ADD|SUB|SUBR)_FPrST0",
+ "(ADD|SUB|SUBR)_FST0r",
+ "(ADD|SUB|SUBR)_FrST0",
"VPBROADCASTBrr",
"VPBROADCASTWrr",
"(V?)PCMPGTQ(Y?)rr",
@@ -978,14 +970,8 @@ def SKLWriteResGroup53 : SchedWriteRes<[
let NumMicroOps = 3;
let ResourceCycles = [1,1,1];
}
-def: InstRW<[SKLWriteResGroup53], (instregex "ISTT_FP16m",
- "ISTT_FP32m",
- "ISTT_FP64m",
- "IST_F16m",
- "IST_F32m",
- "IST_FP16m",
- "IST_FP32m",
- "IST_FP64m")>;
+def: InstRW<[SKLWriteResGroup53], (instregex "IST(T?)_FP(16|32|64)m",
+ "IST_F(16|32)m")>;
def SKLWriteResGroup54 : SchedWriteRes<[SKLPort0156]> {
let Latency = 4;
@@ -1257,9 +1243,7 @@ def SKLWriteResGroup85 : SchedWriteRes<[
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[SKLWriteResGroup85], (instregex "LD_F32m",
- "LD_F64m",
- "LD_F80m",
+def: InstRW<[SKLWriteResGroup85], (instregex "LD_F(32|64|80)m",
"VBROADCASTF128",
"VBROADCASTI128",
"VBROADCASTSDYrm",
@@ -1830,15 +1814,8 @@ def SKLWriteResGroup133 : SchedWriteRes<
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SKLWriteResGroup133], (instregex "ADD_F32m",
- "ADD_F64m",
- "ILD_F16m",
- "ILD_F32m",
- "ILD_F64m",
- "SUBR_F32m",
- "SUBR_F64m",
- "SUB_F32m",
- "SUB_F64m",
+def: InstRW<[SKLWriteResGroup133], (instregex "(ADD|SUB|SUBR)_F(32|64)m",
+ "ILD_F(16|32|64)m",
"VPCMPGTQYrm",
"VPERM2F128rm",
"VPERM2I128rm",
@@ -1954,8 +1931,7 @@ def SKLWriteResGroup146 : SchedWriteRes<
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SKLWriteResGroup146], (instregex "MUL_F32m",
- "MUL_F64m",
+def: InstRW<[SKLWriteResGroup146], (instregex "MUL_F(32|64)m",
"VRCPPSYm",
"VRSQRTPSYm")>;
@@ -2091,12 +2067,7 @@ def SKLWriteResGroup162 : SchedWriteRes<
let NumMicroOps = 3;
let ResourceCycles = [2,1];
}
-def: InstRW<[SKLWriteResGroup162], (instregex "ADD_FI16m",
- "ADD_FI32m",
- "SUBR_FI16m",
- "SUBR_FI32m",
- "SUB_FI16m",
- "SUB_FI32m")>;
+def: InstRW<[SKLWriteResGroup162], (instregex "(ADD|SUB|SUBR)_FI(16|32)m")>;
def SKLWriteResGroup163 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
let Latency = 13;
@@ -2142,8 +2113,7 @@ def SKLWriteResGroup169 : SchedWriteRes<
let NumMicroOps = 3;
let ResourceCycles = [1,1,1];
}
-def: InstRW<[SKLWriteResGroup169], (instregex "MUL_FI16m",
- "MUL_FI32m")>;
+def: InstRW<[SKLWriteResGroup169], (instregex "MUL_FI(16|32)m")>;
def SKLWriteResGroup170 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort15,SKLPort0156]> {
let Latency = 14;
@@ -2345,8 +2315,7 @@ def SKLWriteResGroup196 : SchedWriteRes<
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SKLWriteResGroup196], (instregex "DIV_F32m",
- "DIV_F64m")>;
+def: InstRW<[SKLWriteResGroup196], (instregex "DIV_F(32|64)m")>;
def SKLWriteResGroup196_1 : SchedWriteRes<[SKLPort0, SKLPort23, SKLPort5, SKLPort015]> {
let Latency = 22;
@@ -2409,16 +2378,14 @@ def SKLWriteResGroup202 : SchedWriteRes<
let NumMicroOps = 3;
let ResourceCycles = [1,1,1];
}
-def: InstRW<[SKLWriteResGroup202], (instregex "DIV_FI16m",
- "DIV_FI32m")>;
+def: InstRW<[SKLWriteResGroup202], (instregex "DIV_FI(16|32)m")>;
def SKLWriteResGroup206 : SchedWriteRes<[SKLPort0,SKLPort23]> {
let Latency = 27;
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SKLWriteResGroup206], (instregex "DIVR_F32m",
- "DIVR_F64m")>;
+def: InstRW<[SKLWriteResGroup206], (instregex "DIVR_F(32|64)m")>;
def SKLWriteResGroup207 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23,SKLPort0156]> {
let Latency = 28;
@@ -2432,8 +2399,7 @@ def SKLWriteResGroup208 : SchedWriteRes<
let NumMicroOps = 3;
let ResourceCycles = [1,1,1];
}
-def: InstRW<[SKLWriteResGroup208], (instregex "DIVR_FI16m",
- "DIVR_FI32m")>;
+def: InstRW<[SKLWriteResGroup208], (instregex "DIVR_FI(16|32)m")>;
def SKLWriteResGroup209 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort23,SKLPort06,SKLPort0156]> {
let Latency = 35;
Modified: llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td?rev=331084&r1=331083&r2=331084&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td Fri Apr 27 14:14:19 2018
@@ -1261,9 +1261,9 @@ def SKXWriteResGroup32 : SchedWriteRes<[
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[SKXWriteResGroup32], (instregex "ADD_FPrST0",
- "ADD_FST0r",
- "ADD_FrST0",
+def: InstRW<[SKXWriteResGroup32], (instregex "(ADD|SUB|SUBR)_FPrST0",
+ "(ADD|SUB|SUBR)_FST0r",
+ "(ADD|SUB|SUBR)_FrST0",
"KSHIFTLBri",
"KSHIFTLDri",
"KSHIFTLQri",
@@ -1276,12 +1276,6 @@ def: InstRW<[SKXWriteResGroup32], (instr
"KUNPCKDQrr",
"KUNPCKWDrr",
"PCMPGTQrr",
- "SUBR_FPrST0",
- "SUBR_FST0r",
- "SUBR_FrST0",
- "SUB_FPrST0",
- "SUB_FST0r",
- "SUB_FrST0",
"VALIGNDZ128rri",
"VALIGNDZ256rri",
"VALIGNDZrri",
@@ -1828,14 +1822,8 @@ def SKXWriteResGroup54 : SchedWriteRes<[
let NumMicroOps = 3;
let ResourceCycles = [1,1,1];
}
-def: InstRW<[SKXWriteResGroup54], (instregex "ISTT_FP16m",
- "ISTT_FP32m",
- "ISTT_FP64m",
- "IST_F16m",
- "IST_F32m",
- "IST_FP16m",
- "IST_FP32m",
- "IST_FP64m",
+def: InstRW<[SKXWriteResGroup54], (instregex "IST(T?)_FP(16|32|64)m",
+ "IST_F(16|32)m",
"VPMOVQDZ128mr(b?)",
"VPMOVQDZ256mr(b?)",
"VPMOVQDZmr(b?)")>;
@@ -2277,9 +2265,7 @@ def SKXWriteResGroup89 : SchedWriteRes<[
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[SKXWriteResGroup89], (instregex "LD_F32m",
- "LD_F64m",
- "LD_F80m",
+def: InstRW<[SKXWriteResGroup89], (instregex "LD_F(32|64|80)m",
"VBROADCASTF128",
"VBROADCASTI128",
"VBROADCASTSDYrm",
@@ -3584,15 +3570,8 @@ def SKXWriteResGroup148 : SchedWriteRes<
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SKXWriteResGroup148], (instregex "ADD_F32m",
- "ADD_F64m",
- "ILD_F16m",
- "ILD_F32m",
- "ILD_F64m",
- "SUBR_F32m",
- "SUBR_F64m",
- "SUB_F32m",
- "SUB_F64m",
+def: InstRW<[SKXWriteResGroup148], (instregex "(ADD|SUB|SUBR)_F(32|64)m",
+ "ILD_F(16|32|64)m",
"VALIGNDZ256rm(b?)i",
"VALIGNDZrm(b?)i",
"VALIGNQZ256rm(b?)i",
@@ -3883,8 +3862,7 @@ def SKXWriteResGroup160 : SchedWriteRes<
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SKXWriteResGroup160], (instregex "MUL_F32m",
- "MUL_F64m",
+def: InstRW<[SKXWriteResGroup160], (instregex "MUL_F(32|64)m",
"VRCP14PDZ256m(b?)",
"VRCP14PSZ256m(b?)",
"VRCPPSYm",
@@ -4203,12 +4181,7 @@ def SKXWriteResGroup180 : SchedWriteRes<
let NumMicroOps = 3;
let ResourceCycles = [2,1];
}
-def: InstRW<[SKXWriteResGroup180], (instregex "ADD_FI16m",
- "ADD_FI32m",
- "SUBR_FI16m",
- "SUBR_FI32m",
- "SUB_FI16m",
- "SUB_FI32m",
+def: InstRW<[SKXWriteResGroup180], (instregex "(ADD|SUB|SUBR)_FI(16|32)m",
"VPERMWZ256rm(b?)",
"VPERMWZrm(b?)")>;
@@ -4274,8 +4247,7 @@ def SKXWriteResGroup187 : SchedWriteRes<
let NumMicroOps = 3;
let ResourceCycles = [1,1,1];
}
-def: InstRW<[SKXWriteResGroup187], (instregex "MUL_FI16m",
- "MUL_FI32m")>;
+def: InstRW<[SKXWriteResGroup187], (instregex "MUL_FI(16|32)m")>;
def SKXWriteResGroup188 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> {
let Latency = 14;
@@ -4563,8 +4535,7 @@ def SKXWriteResGroup223 : SchedWriteRes<
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SKXWriteResGroup223], (instregex "DIV_F32m",
- "DIV_F64m")>;
+def: InstRW<[SKXWriteResGroup223], (instregex "DIV_F(32|64)m")>;
def SKXWriteResGroup224 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015,SKXPort0156]> {
let Latency = 22;
@@ -4680,8 +4651,7 @@ def SKXWriteResGroup233 : SchedWriteRes<
let NumMicroOps = 3;
let ResourceCycles = [1,1,1];
}
-def: InstRW<[SKXWriteResGroup233], (instregex "DIV_FI16m",
- "DIV_FI32m")>;
+def: InstRW<[SKXWriteResGroup233], (instregex "DIV_FI(16|32)m")>;
def SKXWriteResGroup234 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015,SKXPort0156]> {
let Latency = 25;
@@ -4716,8 +4686,7 @@ def SKXWriteResGroup239 : SchedWriteRes<
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SKXWriteResGroup239], (instregex "DIVR_F32m",
- "DIVR_F64m")>;
+def: InstRW<[SKXWriteResGroup239], (instregex "DIVR_F(32|64)m")>;
def SKXWriteResGroup240 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015,SKXPort0156]> {
let Latency = 27;
@@ -4746,8 +4715,7 @@ def SKXWriteResGroup243 : SchedWriteRes<
let NumMicroOps = 3;
let ResourceCycles = [1,1,1];
}
-def: InstRW<[SKXWriteResGroup243], (instregex "DIVR_FI16m",
- "DIVR_FI32m")>;
+def: InstRW<[SKXWriteResGroup243], (instregex "DIVR_FI(16|32)m")>;
def SKXWriteResGroup244 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort5,SKXFPDivider]> {
let Latency = 30;
Modified: llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td?rev=331084&r1=331083&r2=331084&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td (original)
+++ llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td Fri Apr 27 14:14:19 2018
@@ -827,8 +827,7 @@ def ZnWriteFPU02 : SchedWriteRes<[ZnAGU,
// FCOMI(P) FUCOMI(P).
// m.
-def : InstRW<[ZnWriteFPU02], (instregex "COM_FIr", "COM_FIPr", "UCOM_FIr",
- "UCOM_FIPr")>;
+def : InstRW<[ZnWriteFPU02], (instrs COM_FIPr, COM_FIr, UCOM_FIPr, UCOM_FIr)>;
def ZnWriteFPU03 : SchedWriteRes<[ZnAGU, ZnFPU03]>
{
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