[llvm] r331050 - [mips] Analyze and provide selection patterns microMIPSR6 branches
Simon Dardis via llvm-commits
llvm-commits at lists.llvm.org
Fri Apr 27 08:49:49 PDT 2018
Author: sdardis
Date: Fri Apr 27 08:49:49 2018
New Revision: 331050
URL: http://llvm.org/viewvc/llvm-project?rev=331050&view=rev
Log:
[mips] Analyze and provide selection patterns microMIPSR6 branches
These branches were previously unanalyzable and unselectable. Add them and
recognize how to generate their inverses.
Reviewers: smaksimovic, atanasyan, abeserminji
Differential Revision: https://reviews.llvm.org/D46113
Modified:
llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td
llvm/trunk/lib/Target/Mips/MipsSEInstrInfo.cpp
llvm/trunk/test/CodeGen/Mips/longbranch.ll
Modified: llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td?rev=331050&r1=331049&r2=331050&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td Fri Apr 27 08:49:49 2018
@@ -1725,3 +1725,37 @@ def : MipsPat<(MipsTailCall (iPTR tgloba
def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
(TAILCALL_MMR6 texternalsym:$dst)>, ISA_MICROMIPS32R6;
+
+def : MipsPat<(brcond (i32 (setne GPR32:$lhs, 0)), bb:$dst),
+ (BNEZC_MMR6 GPR32:$lhs, bb:$dst)>, ISA_MICROMIPS32R6;
+def : MipsPat<(brcond (i32 (seteq GPR32:$lhs, 0)), bb:$dst),
+ (BEQZC_MMR6 GPR32:$lhs, bb:$dst)>, ISA_MICROMIPS32R6;
+
+def : MipsPat<(brcond (i32 (setge GPR32:$lhs, GPR32:$rhs)), bb:$dst),
+ (BEQZC_MMR6 (SLT_MM GPR32:$lhs, GPR32:$rhs), bb:$dst)>,
+ ISA_MICROMIPS32R6;
+def : MipsPat<(brcond (i32 (setuge GPR32:$lhs, GPR32:$rhs)), bb:$dst),
+ (BEQZC_MMR6 (SLTu_MM GPR32:$lhs, GPR32:$rhs), bb:$dst)>,
+ ISA_MICROMIPS32R6;
+def : MipsPat<(brcond (i32 (setge GPR32:$lhs, immSExt16:$rhs)), bb:$dst),
+ (BEQZC_MMR6 (SLTi_MM GPR32:$lhs, immSExt16:$rhs), bb:$dst)>,
+ ISA_MICROMIPS32R6;
+def : MipsPat<(brcond (i32 (setuge GPR32:$lhs, immSExt16:$rhs)), bb:$dst),
+ (BEQZC_MMR6 (SLTiu_MM GPR32:$lhs, immSExt16:$rhs), bb:$dst)>,
+ ISA_MICROMIPS32R6;
+def : MipsPat<(brcond (i32 (setgt GPR32:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
+ (BEQZC_MMR6 (SLTi_MM GPR32:$lhs, (Plus1 imm:$rhs)), bb:$dst)>,
+ ISA_MICROMIPS32R6;
+def : MipsPat<(brcond (i32 (setugt GPR32:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
+ (BEQZC_MMR6 (SLTiu_MM GPR32:$lhs, (Plus1 imm:$rhs)), bb:$dst)>,
+ ISA_MICROMIPS32R6;
+
+def : MipsPat<(brcond (i32 (setle GPR32:$lhs, GPR32:$rhs)), bb:$dst),
+ (BEQZC_MMR6 (SLT_MM GPR32:$rhs, GPR32:$lhs), bb:$dst)>,
+ ISA_MICROMIPS32R6;
+def : MipsPat<(brcond (i32 (setule GPR32:$lhs, GPR32:$rhs)), bb:$dst),
+ (BEQZC_MMR6 (SLTu_MM GPR32:$rhs, GPR32:$lhs), bb:$dst)>,
+ ISA_MICROMIPS32R6;
+
+def : MipsPat<(brcond GPR32:$cond, bb:$dst),
+ (BNEZC_MMR6 GPR32:$cond, bb:$dst)>, ISA_MICROMIPS32R6;
Modified: llvm/trunk/lib/Target/Mips/MipsSEInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSEInstrInfo.cpp?rev=331050&r1=331049&r2=331050&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsSEInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsSEInstrInfo.cpp Fri Apr 27 08:49:49 2018
@@ -445,6 +445,14 @@ unsigned MipsSEInstrInfo::getOppositeBra
case Mips::BGEZC: return Mips::BLTZC;
case Mips::BLTZC: return Mips::BGEZC;
case Mips::BLEZC: return Mips::BGTZC;
+ case Mips::BEQZC_MMR6: return Mips::BNEZC_MMR6;
+ case Mips::BNEZC_MMR6: return Mips::BEQZC_MMR6;
+ case Mips::BEQC_MMR6: return Mips::BNEC_MMR6;
+ case Mips::BNEC_MMR6: return Mips::BEQC_MMR6;
+ case Mips::BGTZC_MMR6: return Mips::BLEZC_MMR6;
+ case Mips::BGEZC_MMR6: return Mips::BLTZC_MMR6;
+ case Mips::BLTZC_MMR6: return Mips::BGEZC_MMR6;
+ case Mips::BLEZC_MMR6: return Mips::BGTZC_MMR6;
case Mips::BEQZC64: return Mips::BNEZC64;
case Mips::BNEZC64: return Mips::BEQZC64;
case Mips::BEQC64: return Mips::BNEC64;
@@ -553,7 +561,13 @@ unsigned MipsSEInstrInfo::getAnalyzableB
Opc == Mips::BGTZC64 || Opc == Mips::BGEZC64 ||
Opc == Mips::BLTZC64 || Opc == Mips::BLEZC64 || Opc == Mips::BC ||
Opc == Mips::BBIT0 || Opc == Mips::BBIT1 || Opc == Mips::BBIT032 ||
- Opc == Mips::BBIT132) ? Opc : 0;
+ Opc == Mips::BBIT132 || Opc == Mips::BC_MMR6 ||
+ Opc == Mips::BEQC_MMR6 || Opc == Mips::BNEC_MMR6 ||
+ Opc == Mips::BLTC_MMR6 || Opc == Mips::BGEC_MMR6 ||
+ Opc == Mips::BLTUC_MMR6 || Opc == Mips::BGEUC_MMR6 ||
+ Opc == Mips::BGTZC_MMR6 || Opc == Mips::BLEZC_MMR6 ||
+ Opc == Mips::BGEZC_MMR6 || Opc == Mips::BLTZC_MMR6 ||
+ Opc == Mips::BEQZC_MMR6 || Opc == Mips::BNEZC_MMR6) ? Opc : 0;
}
void MipsSEInstrInfo::expandRetRA(MachineBasicBlock &MBB,
Modified: llvm/trunk/test/CodeGen/Mips/longbranch.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/longbranch.ll?rev=331050&r1=331049&r2=331050&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/longbranch.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/longbranch.ll Fri Apr 27 08:49:49 2018
@@ -249,14 +249,12 @@ define void @test1(i32 signext %s) {
; MICROMIPSR6STATIC: # %bb.0: # %entry
; MICROMIPSR6STATIC-NEXT: bnezc $4, $BB0_2
; MICROMIPSR6STATIC-NEXT: # %bb.1: # %entry
-; MICROMIPSR6STATIC-NEXT: bc $BB0_4
-; MICROMIPSR6STATIC-NEXT: $BB0_2: # %entry
; MICROMIPSR6STATIC-NEXT: bc $BB0_3
-; MICROMIPSR6STATIC-NEXT: $BB0_3: # %then
+; MICROMIPSR6STATIC-NEXT: $BB0_2: # %then
; MICROMIPSR6STATIC-NEXT: lui $1, %hi(x)
; MICROMIPSR6STATIC-NEXT: li16 $2, 1
; MICROMIPSR6STATIC-NEXT: sw $2, %lo(x)($1)
-; MICROMIPSR6STATIC-NEXT: $BB0_4: # %end
+; MICROMIPSR6STATIC-NEXT: $BB0_3: # %end
; MICROMIPSR6STATIC-NEXT: jrc $ra
;
; MICROMIPSR6PIC-LABEL: test1:
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