[PATCH] D46158: [DAGCombiner] Set the right SDLoc on a newly-created sextload (4/N)

[Nirav Dave via Phabricator via llvm-commits]

niravd added a comment.

The additional register pressure is unfortunate but is unrelated. Before I LGTM, I just wanted an additional agreement that the regression is vector-shuffle-variable tests isn't justification to delay.


https://reviews.llvm.org/D46158