[llvm] r330952 - [mips] Correct the definitions of some control instructions
Simon Dardis via llvm-commits
llvm-commits at lists.llvm.org
Thu Apr 26 09:06:34 PDT 2018
Author: sdardis
Date: Thu Apr 26 09:06:34 2018
New Revision: 330952
URL: http://llvm.org/viewvc/llvm-project?rev=330952&view=rev
Log:
[mips] Correct the definitions of some control instructions
Correct the definitions of ei, di, eret, deret, wait, syscall and break.
Also provide microMIPS specific aliases to match the MIPS aliases.
Additionally correct the definition of the wait instruction so that
it is present in the instruction mapping tables.
Reviewers: smaksimovic, abeserminji, atanasyan
Differential Revision: https://reviews.llvm.org/D45939
Modified:
llvm/trunk/lib/Target/Mips/MicroMipsInstrFormats.td
llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td
llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
llvm/trunk/test/MC/Mips/micromips-control-instructions.s
llvm/trunk/test/MC/Mips/mips-control-instructions.s
Modified: llvm/trunk/lib/Target/Mips/MicroMipsInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMipsInstrFormats.td?rev=330952&r1=330951&r2=330952&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MicroMipsInstrFormats.td (original)
+++ llvm/trunk/lib/Target/Mips/MicroMipsInstrFormats.td Thu Apr 26 09:06:34 2018
@@ -630,7 +630,7 @@ class SYS_FM_MM : MMArch {
let Inst{5-0} = 0x3c;
}
-class WAIT_FM_MM {
+class WAIT_FM_MM : MMArch {
bits<10> code_;
bits<32> Inst;
Modified: llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td?rev=330952&r1=330951&r2=330952&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td Thu Apr 26 09:06:34 2018
@@ -967,17 +967,18 @@ let DecoderNamespace = "MicroMips" in {
let DecoderMethod = "DecodeSyncI_MM" in
def SYNCI_MM : MMRel, SYNCI_FT<"synci", mem_mm_16>, SYNCI_FM_MM,
ISA_MICROMIPS32_NOT_MIPS32R6;
- let Predicates = [InMicroMips] in {
- def BREAK_MM : MMRel, BRK_FT<"break">, BRK_FM_MM;
- def SYSCALL_MM : MMRel, SYS_FT<"syscall", uimm10, II_SYSCALL>, SYS_FM_MM;
- def WAIT_MM : WaitMM<"wait">, WAIT_FM_MM;
- def ERET_MM : MMRel, ER_FT<"eret", II_ERET>, ER_FM_MM<0x3cd>;
- def DERET_MM : MMRel, ER_FT<"deret", II_DERET>, ER_FM_MM<0x38d>;
+ def BREAK_MM : MMRel, BRK_FT<"break">, BRK_FM_MM, ISA_MICROMIPS;
+ def SYSCALL_MM : MMRel, SYS_FT<"syscall", uimm10, II_SYSCALL>, SYS_FM_MM,
+ ISA_MICROMIPS;
+ def WAIT_MM : MMRel, WaitMM<"wait">, WAIT_FM_MM, ISA_MICROMIPS;
+ def ERET_MM : MMRel, ER_FT<"eret", II_ERET>, ER_FM_MM<0x3cd>,
+ ISA_MICROMIPS;
+ def DERET_MM : MMRel, ER_FT<"deret", II_DERET>, ER_FM_MM<0x38d>,
+ ISA_MICROMIPS;
def EI_MM : MMRel, DEI_FT<"ei", GPR32Opnd, II_EI>, EI_FM_MM<0x15d>,
- ISA_MIPS32R2;
+ ISA_MICROMIPS;
def DI_MM : MMRel, DEI_FT<"di", GPR32Opnd, II_DI>, EI_FM_MM<0x11d>,
- ISA_MIPS32R2;
- }
+ ISA_MICROMIPS;
/// Trap Instructions
def TEQ_MM : MMRel, TEQ_FT<"teq", GPR32Opnd, uimm4, II_TEQ>, TEQ_FM_MM<0x0>,
@@ -1174,11 +1175,11 @@ let Predicates = [InMicroMips] in {
def UDIV_MM_Pseudo : MultDivPseudo<UDIV_MM, ACC64, GPR32Opnd, MipsDivRemU,
II_DIVU, 0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6;
- def : MipsInstAlias<"wait", (WAIT_MM 0x0), 1>;
+ def : MipsInstAlias<"wait", (WAIT_MM 0x0), 1>, ISA_MICROMIPS;
def : MipsInstAlias<"nop", (SLL_MM ZERO, ZERO, 0), 1>;
def : MipsInstAlias<"nop", (MOVE16_MM ZERO, ZERO), 1>;
- def : MipsInstAlias<"ei", (EI_MM ZERO), 1>, ISA_MIPS32R2;
- def : MipsInstAlias<"di", (DI_MM ZERO), 1>, ISA_MIPS32R2;
+ def : MipsInstAlias<"ei", (EI_MM ZERO), 1>, ISA_MICROMIPS;
+ def : MipsInstAlias<"di", (DI_MM ZERO), 1>, ISA_MICROMIPS;
def : MipsInstAlias<"teq $rs, $rt",
(TEQ_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
def : MipsInstAlias<"tge $rs, $rt",
@@ -1223,7 +1224,7 @@ let Predicates = [InMicroMips] in {
(SRL_MM GPR32Opnd:$rd, GPR32Opnd:$rd, uimm5:$shamt), 0>;
def : MipsInstAlias<"rotr $rt, $imm",
(ROTR_MM GPR32Opnd:$rt, GPR32Opnd:$rt, uimm5:$imm), 0>;
- def : MipsInstAlias<"syscall", (SYSCALL_MM 0), 1>;
+ def : MipsInstAlias<"syscall", (SYSCALL_MM 0), 1>, ISA_MICROMIPS;
def : MipsInstAlias<"sync", (SYNC_MM 0), 1>, ISA_MICROMIPS;
@@ -1257,4 +1258,7 @@ let Predicates = [InMicroMips] in {
ISA_MIPS32R2_NOT_32R6_64R6;
def : MipsInstAlias<"seb $rd", (SEB_MM GPR32Opnd:$rd, GPR32Opnd:$rd), 0>,
ISA_MIPS32R2_NOT_32R6_64R6;
+ def : MipsInstAlias<"break", (BREAK_MM 0, 0), 1>, ISA_MICROMIPS;
+ def : MipsInstAlias<"break $imm", (BREAK_MM uimm10:$imm, 0), 1>,
+ ISA_MICROMIPS;
}
Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=330952&r1=330951&r2=330952&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Thu Apr 26 09:06:34 2018
@@ -2083,28 +2083,24 @@ let AdditionalPredicates = [NotInMicroMi
}
let AdditionalPredicates = [NotInMicroMips] in {
-def BREAK : MMRel, StdMMR6Rel, BRK_FT<"break">, BRK_FM<0xd>;
-def SYSCALL : MMRel, SYS_FT<"syscall", uimm20, II_SYSCALL>, SYS_FM<0xc>;
-}
-def TRAP : TrapBase<BREAK>;
-let AdditionalPredicates = [NotInMicroMips] in {
-def SDBBP : MMRel, SYS_FT<"sdbbp", uimm20, II_SDBBP>, SDBBP_FM, ISA_MIPS32_NOT_32R6_64R6;
-}
+ def BREAK : MMRel, StdMMR6Rel, BRK_FT<"break">, BRK_FM<0xd>, ISA_MIPS1;
+ def SYSCALL : MMRel, SYS_FT<"syscall", uimm20, II_SYSCALL>, SYS_FM<0xc>,
+ ISA_MIPS1;
+ def TRAP : TrapBase<BREAK>, ISA_MIPS1;
+ def SDBBP : MMRel, SYS_FT<"sdbbp", uimm20, II_SDBBP>, SDBBP_FM,
+ ISA_MIPS32_NOT_32R6_64R6;
-let AdditionalPredicates = [NotInMicroMips] in {
def ERET : MMRel, ER_FT<"eret", II_ERET>, ER_FM<0x18, 0x0>, INSN_MIPS3_32;
- def ERETNC : MMRel, ER_FT<"eretnc", II_ERETNC>, ER_FM<0x18, 0x1>, ISA_MIPS32R5;
+ def ERETNC : MMRel, ER_FT<"eretnc", II_ERETNC>, ER_FM<0x18, 0x1>,
+ ISA_MIPS32R5;
def DERET : MMRel, ER_FT<"deret", II_DERET>, ER_FM<0x1f, 0x0>, ISA_MIPS32;
-}
-let AdditionalPredicates = [NotInMicroMips] in {
- def EI : MMRel, StdMMR6Rel, DEI_FT<"ei", GPR32Opnd, II_EI>, EI_FM<1>, ISA_MIPS32R2;
- def DI : MMRel, StdMMR6Rel, DEI_FT<"di", GPR32Opnd, II_DI>, EI_FM<0>, ISA_MIPS32R2;
-}
+ def EI : MMRel, StdMMR6Rel, DEI_FT<"ei", GPR32Opnd, II_EI>, EI_FM<1>,
+ ISA_MIPS32R2;
+ def DI : MMRel, StdMMR6Rel, DEI_FT<"di", GPR32Opnd, II_DI>, EI_FM<0>,
+ ISA_MIPS32R2;
-let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
- AdditionalPredicates = [NotInMicroMips] in {
-def WAIT : WAIT_FT<"wait">, WAIT_FM;
+ def WAIT : MMRel, StdMMR6Rel, WAIT_FT<"wait">, WAIT_FM, INSN_MIPS3_32;
}
let AdditionalPredicates = [NotInMicroMips] in {
@@ -2116,7 +2112,7 @@ def SC : SCBase<"sc", GPR32Opnd>, LW_FM<
/// Jump and Branch Instructions
def J : MMRel, JumpFJ<jmptarget, "j", br, bb, "j">, FJ<2>,
AdditionalRequires<[RelocNotPIC, NotInMicroMips]>, IsBranch;
-def JR : MMRel, IndirectBranch<"jr", GPR32Opnd>, MTLO_FM<8>, ISA_MIPS1_NOT_32R6_64R6;
+def JR : MMRel, IndirectBranch<"jr", GPR32Opnd>, MTLO_FM<8>, ISA_MIPS1_NOT_32R6_64R6;
def BEQ : MMRel, CBranch<"beq", brtarget, seteq, GPR32Opnd>, BEQ_FM<4>;
def BEQL : MMRel, CBranchLikely<"beql", brtarget, GPR32Opnd>,
BEQ_FM<20>, ISA_MIPS2_NOT_32R6_64R6;
@@ -2589,16 +2585,13 @@ def : MipsInstAlias<"beqz $rs,$offset",
def : MipsInstAlias<"beqzl $rs,$offset",
(BEQL GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
let AdditionalPredicates = [NotInMicroMips] in {
- def : MipsInstAlias<"syscall", (SYSCALL 0), 1>;
-}
+ def : MipsInstAlias<"syscall", (SYSCALL 0), 1>, ISA_MIPS1;
-def : MipsInstAlias<"break", (BREAK 0, 0), 1>;
-def : MipsInstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>;
-let AdditionalPredicates = [NotInMicroMips] in {
+ def : MipsInstAlias<"break", (BREAK 0, 0), 1>, ISA_MIPS1;
+ def : MipsInstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>, ISA_MIPS1;
def : MipsInstAlias<"ei", (EI ZERO), 1>, ISA_MIPS32R2;
def : MipsInstAlias<"di", (DI ZERO), 1>, ISA_MIPS32R2;
-}
-let AdditionalPredicates = [NotInMicroMips] in {
+
def : MipsInstAlias<"teq $rs, $rt",
(TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
def : MipsInstAlias<"tge $rs, $rt",
Modified: llvm/trunk/test/MC/Mips/micromips-control-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips-control-instructions.s?rev=330952&r1=330951&r2=330952&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/micromips-control-instructions.s (original)
+++ llvm/trunk/test/MC/Mips/micromips-control-instructions.s Thu Apr 26 09:06:34 2018
@@ -1,6 +1,6 @@
-# RUN: llvm-mc %s -triple=mipsel -show-encoding -mcpu=mips32r2 -mattr=micromips \
+# RUN: llvm-mc %s -triple=mipsel -show-encoding -mcpu=mips32r2 -mattr=micromips -show-inst \
# RUN: | FileCheck -check-prefix=CHECK-EL %s
-# RUN: llvm-mc %s -triple=mips -show-encoding -mcpu=mips32r2 -mattr=micromips \
+# RUN: llvm-mc %s -triple=mips -show-encoding -mcpu=mips32r2 -mattr=micromips -show-inst \
# RUN: | FileCheck -check-prefix=CHECK-EB %s
# Check that the assembler can handle the documented syntax
# for control instructions.
@@ -21,20 +21,31 @@
# CHECK-EL: ehb # encoding: [0x00,0x00,0x00,0x18]
# CHECK-EL: pause # encoding: [0x00,0x00,0x00,0x28]
# CHECK-EL: break # encoding: [0x00,0x00,0x07,0x00]
+# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} BREAK_MM
# CHECK-EL: break 7 # encoding: [0x07,0x00,0x07,0x00]
+# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} BREAK_MM
# CHECK-EL: break 7, 5 # encoding: [0x07,0x00,0x47,0x01]
+# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} BREAK_MM
# CHECK-EL: syscall # encoding: [0x00,0x00,0x7c,0x8b]
+# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} SYSCALL_MM
# CHECK-EL: syscall 396 # encoding: [0x8c,0x01,0x7c,0x8b]
+# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} SYSCALL_MM
# CHECK-EL: eret # encoding: [0x00,0x00,0x7c,0xf3]
+# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} ERET_MM
# CHECK-EL: deret # encoding: [0x00,0x00,0x7c,0xe3]
+# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} DERET_MM
# CHECK-EL: di # encoding: [0x00,0x00,0x7c,0x47]
-# CHECK-EL: di # encoding: [0x00,0x00,0x7c,0x47]
+# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} DI_MM
# CHECK-EL: di $10 # encoding: [0x0a,0x00,0x7c,0x47]
+# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} DI_MM
# CHECK-EL: ei # encoding: [0x00,0x00,0x7c,0x57]
-# CHECK-EL: ei # encoding: [0x00,0x00,0x7c,0x57]
+# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} EI_MM
# CHECK-EL: ei $10 # encoding: [0x0a,0x00,0x7c,0x57]
+# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} EI_MM
# CHECK-EL: wait # encoding: [0x00,0x00,0x7c,0x93]
+# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} WAIT_MM
# CHECK-EL: wait 17 # encoding: [0x11,0x00,0x7c,0x93]
+# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} WAIT_MM
# CHECK-EL: tlbp # encoding: [0x00,0x00,0x7c,0x03]
# CHECK-EL: tlbr # encoding: [0x00,0x00,0x7c,0x13]
# CHECK-EL: tlbwi # encoding: [0x00,0x00,0x7c,0x23]
Modified: llvm/trunk/test/MC/Mips/mips-control-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips-control-instructions.s?rev=330952&r1=330951&r2=330952&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips-control-instructions.s (original)
+++ llvm/trunk/test/MC/Mips/mips-control-instructions.s Thu Apr 26 09:06:34 2018
@@ -1,20 +1,24 @@
-# RUN: llvm-mc %s -triple=mips-unknown-unknown -show-encoding -mcpu=mips32r2 | \
+# RUN: llvm-mc %s -triple=mips-unknown-unknown -show-encoding -mcpu=mips32r2 -show-inst| \
# RUN: FileCheck -check-prefix=CHECK32 %s
-# RUN: llvm-mc %s -triple=mips64-unknown-unknown -show-encoding -mcpu=mips64r2 \
+# RUN: llvm-mc %s -triple=mips64-unknown-unknown -show-encoding -mcpu=mips64r2 -show-inst \
# RUN: | FileCheck -check-prefix=CHECK64 %s
# CHECK32: break # encoding: [0x00,0x00,0x00,0x0d]
+# CHECK32-NEXT: # <MCInst #{{[0-9]+}} BREAK
# CHECK32: break 7 # encoding: [0x00,0x07,0x00,0x0d]
# CHECK32: break 7, 5 # encoding: [0x00,0x07,0x01,0x4d]
# CHECK32: eret # encoding: [0x42,0x00,0x00,0x18]
+# CHECK32-NEXT: # <MCInst #{{[0-9]+}} ERET
# CHECK32: deret # encoding: [0x42,0x00,0x00,0x1f]
+# CHECK32-NEXT: # <MCInst #{{[0-9]+}} DERET
# CHECK32: di # encoding: [0x41,0x60,0x60,0x00]
-# CHECK32: di # encoding: [0x41,0x60,0x60,0x00]
+# CHECK32-NEXT: # <MCInst #{{[0-9]+}} DI
# CHECK32: di $10 # encoding: [0x41,0x6a,0x60,0x00]
# CHECK32: ei # encoding: [0x41,0x60,0x60,0x20]
-# CHECK32: ei # encoding: [0x41,0x60,0x60,0x20]
+# CHECK32-NEXT: # <MCInst #{{[0-9]+}} EI
# CHECK32: ei $10 # encoding: [0x41,0x6a,0x60,0x20]
# CHECK32: wait # encoding: [0x42,0x00,0x00,0x20]
+# CHECK32-NEXT: # <MCInst #{{[0-9]+}} WAIT
# CHECK32: teq $zero, $3 # encoding: [0x00,0x03,0x00,0x34]
# CHECK32: teq $zero, $3, 1 # encoding: [0x00,0x03,0x00,0x74]
# CHECK32: teqi $3, 1 # encoding: [0x04,0x6c,0x00,0x01]
@@ -35,17 +39,21 @@
# CHECK32: tnei $3, 1023 # encoding: [0x04,0x6e,0x03,0xff]
# CHECK64: break # encoding: [0x00,0x00,0x00,0x0d]
+# CHECK64-NEXT: # <MCInst #{{[0-9]+}} BREAK
# CHECK64: break 7 # encoding: [0x00,0x07,0x00,0x0d]
# CHECK64: break 7, 5 # encoding: [0x00,0x07,0x01,0x4d]
# CHECK64: eret # encoding: [0x42,0x00,0x00,0x18]
+# CHECK64-NEXT: # <MCInst #{{[0-9]+}} ERET
# CHECK64: deret # encoding: [0x42,0x00,0x00,0x1f]
+# CHECK64-NEXT: # <MCInst #{{[0-9]+}} DERET
# CHECK64: di # encoding: [0x41,0x60,0x60,0x00]
-# CHECK64: di # encoding: [0x41,0x60,0x60,0x00]
+# CHECK64-NEXT: # <MCInst #{{[0-9]+}} DI
# CHECK64: di $10 # encoding: [0x41,0x6a,0x60,0x00]
# CHECK64: ei # encoding: [0x41,0x60,0x60,0x20]
-# CHECK64: ei # encoding: [0x41,0x60,0x60,0x20]
+# CHECK64-NEXT: # <MCInst #{{[0-9]+}} EI
# CHECK64: ei $10 # encoding: [0x41,0x6a,0x60,0x20]
# CHECK64: wait # encoding: [0x42,0x00,0x00,0x20]
+# CHECK64-NEXT: # <MCInst #{{[0-9]+}} WAIT
# CHECK64: teq $zero, $3 # encoding: [0x00,0x03,0x00,0x34]
# CHECK64: teq $zero, $3, 1 # encoding: [0x00,0x03,0x00,0x74]
# CHECK64: teqi $3, 1 # encoding: [0x04,0x6c,0x00,0x01]
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