[llvm] r330950 - [x86] add tests to show potential opt-out of ftrunc optimization; NFC

[Sanjay Patel via llvm-commits]

Author: spatel
Date: Thu Apr 26 08:36:15 2018
New Revision: 330950

URL: http://llvm.org/viewvc/llvm-project?rev=330950&view=rev
Log:
[x86] add tests to show potential opt-out of ftrunc optimization; NFC

This is another preliminary step for disabling this transform as 
discussed in the post-commit thread for:
rL330437
I'm using one of the names suggested there for the attribute, but 
we can fix that up as needed once the clang side of this is sorted 
out. 

Modified:
    llvm/trunk/test/CodeGen/X86/ftrunc.ll

Modified: llvm/trunk/test/CodeGen/X86/ftrunc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/ftrunc.ll?rev=330950&r1=330949&r2=330950&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/ftrunc.ll (original)
+++ llvm/trunk/test/CodeGen/X86/ftrunc.ll Thu Apr 26 08:36:15 2018
@@ -356,3 +356,54 @@ define <4 x double> @trunc_signed_v4f64(
   ret <4 x double> %r
 }
 
+; FIXME: The attribute name is subject to change, but the fold may be
+; guarded to allow existing code to continue working based on its
+; assumptions of float->int overflow.
+
+define float @trunc_unsigned_f32_disable_via_attr(float %x) #1 {
+; SSE2-LABEL: trunc_unsigned_f32_disable_via_attr:
+; SSE2:       # %bb.0:
+; SSE2-NEXT:    cvttss2si %xmm0, %rax
+; SSE2-NEXT:    movl %eax, %eax
+; SSE2-NEXT:    xorps %xmm0, %xmm0
+; SSE2-NEXT:    cvtsi2ssq %rax, %xmm0
+; SSE2-NEXT:    retq
+;
+; SSE41-LABEL: trunc_unsigned_f32_disable_via_attr:
+; SSE41:       # %bb.0:
+; SSE41-NEXT:    roundss $11, %xmm0, %xmm0
+; SSE41-NEXT:    retq
+;
+; AVX1-LABEL: trunc_unsigned_f32_disable_via_attr:
+; AVX1:       # %bb.0:
+; AVX1-NEXT:    vroundss $11, %xmm0, %xmm0, %xmm0
+; AVX1-NEXT:    retq
+  %i = fptoui float %x to i32
+  %r = uitofp i32 %i to float
+  ret float %r
+}
+
+define double @trunc_signed_f64_disable_via_attr(double %x) #1 {
+; SSE2-LABEL: trunc_signed_f64_disable_via_attr:
+; SSE2:       # %bb.0:
+; SSE2-NEXT:    cvttsd2si %xmm0, %rax
+; SSE2-NEXT:    xorps %xmm0, %xmm0
+; SSE2-NEXT:    cvtsi2sdq %rax, %xmm0
+; SSE2-NEXT:    retq
+;
+; SSE41-LABEL: trunc_signed_f64_disable_via_attr:
+; SSE41:       # %bb.0:
+; SSE41-NEXT:    roundsd $11, %xmm0, %xmm0
+; SSE41-NEXT:    retq
+;
+; AVX1-LABEL: trunc_signed_f64_disable_via_attr:
+; AVX1:       # %bb.0:
+; AVX1-NEXT:    vroundsd $11, %xmm0, %xmm0, %xmm0
+; AVX1-NEXT:    retq
+  %i = fptosi double %x to i64
+  %r = sitofp i64 %i to double
+  ret double %r
+}
+
+attributes #1 = { nounwind "fp-cast-overflow-workaround"="true" }
+