[PATCH] D46111: [ARM] Enable misched for R52.

[Dave Green via Phabricator via llvm-commits]

dmgreen created this revision.
dmgreen added reviewers: javed.absar, fhahn, samparker.
Herald added subscribers: chrib, kristof.beyls.

Back when the R52 schedule was added in https://reviews.llvm.org/rL286949, there was no way
to enable machine schedules in ARM for specific cores. Since then a
target feature has been added. This enables the feature for R52, removing
the need manually specify compiler flags.


https://reviews.llvm.org/D46111

Files:
  lib/Target/ARM/ARM.td
  test/CodeGen/ARM/cortexr52-misched-basic.ll


Index: test/CodeGen/ARM/cortexr52-misched-basic.ll
===================================================================
--- test/CodeGen/ARM/cortexr52-misched-basic.ll
+++ test/CodeGen/ARM/cortexr52-misched-basic.ll
@@ -1,5 +1,5 @@
 ; REQUIRES: asserts
-; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-r52 -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s --check-prefix=CHECK --check-prefix=R52_SCHED
+; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-r52 -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s --check-prefix=CHECK --check-prefix=R52_SCHED
 ; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=generic    -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s --check-prefix=CHECK --check-prefix=GENERIC
 ;
 ; Check the latency for instructions for both generic and cortex-r52.
Index: lib/Target/ARM/ARM.td
===================================================================
--- lib/Target/ARM/ARM.td
+++ lib/Target/ARM/ARM.td
@@ -999,6 +999,7 @@
                                                          FeatureCRC]>;
 
 def : ProcessorModel<"cortex-r52", CortexR52Model,      [ARMv8r, ProcR52,
+                                                         FeatureUseMISched,
                                                          FeatureFPAO]>;
 
 //===----------------------------------------------------------------------===//


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