[PATCH] D45953: [AArch64][SVE] Asm: Support for gather LD1/LDFF1 (scalar + vector (32bit elts, scaled)) load instructions.

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen added inline comments.


================
Comment at: lib/Target/AArch64/SVEInstrFormats.td:733
 
+class sve_mem_32b_gld_sv<bits<4> opc, bit xs, string asm,
+                         RegisterOperand zprext>
----------------
fhahn wrote:
> There seems to be a 1 line difference only between this class and `sve_mem_32b_gld_vs` added in D45952. I think it would be great if we could have one class for those similar cases if possible. It takes parameters already, so I think it would make sense to add a new one?
Thanks for the suggestion, I have merged these classes (also for 64b) into one, reducing the size of the diff. The change is made in D46023 .


https://reviews.llvm.org/D45953