[PATCH] D45994: AMDGPU/GlobalISel: Enable TableGen'd instruction selector

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


================
Comment at: lib/Target/AMDGPU/SIRegisterInfo.cpp:1574
+    return RB->getID() == AMDGPU::VGPRRegBankID ? &AMDGPU::VGPR_32RegClass :
+                                                  &AMDGPU::SReg_32RegClass;
+  case 64:
----------------
Should this be the allocatable SReg_32_XM0?


================
Comment at: lib/Target/AMDGPU/SIRegisterInfo.cpp:1577
+    return RB->getID() == AMDGPU::VGPRRegBankID ? &AMDGPU::VReg_64RegClass :
+                                                   &AMDGPU::SReg_64RegClass;
+  default:
----------------
Same for XEXEC


================
Comment at: test/CodeGen/AMDGPU/GlobalISel/inst-select-or.mir:4
+--- |
+  define amdgpu_kernel void @or(i32 addrspace(1)* %global0) {ret void}
+...
----------------
should be able to drop this if the calling convention doesn't matter


Repository:
  rL LLVM

https://reviews.llvm.org/D45994