[PATCH] D45995: [DAGCombiner] Set the right SDLoc on a newly-created zextload

[Adrian Prantl via Phabricator via llvm-commits]

aprantl requested changes to this revision.
aprantl added a comment.
This revision now requires changes to proceed.

Wow that's a surprising amount of churn! The change itself looks good, I would just prefer a smaller testcase if that is possible.



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Comment at: test/CodeGen/AArch64/arm64-aapcs.ll:31
+; CHECK-LABEL: test_stack_slots:
+; CHECK-DAG: ldr w[[ext1:[0-9]+]], [sp, #24]
+; CHECK-DAG: ldrh w[[ext2:[0-9]+]], [sp, #16]
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So the order of these instructions is irrelevant?


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Comment at: test/CodeGen/X86/fold-zext-trunc-dbginfo.ll:1
+; RUN: llc < %s -O0 -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -stop-after livedebugvalues -o - | FileCheck %s
+
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I'm not convinced if this huge test adds anything on top of all the other tests. Could you either remove it or replace it with a function that really only consists of the affected pattern?


https://reviews.llvm.org/D45995