[llvm] r330662 - [X86] Remove unnecessary vector memory folded InstRW overrides.
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Mon Apr 23 15:45:04 PDT 2018
Author: rksimon
Date: Mon Apr 23 15:45:04 2018
New Revision: 330662
URL: http://llvm.org/viewvc/llvm-project?rev=330662&view=rev
Log:
[X86] Remove unnecessary vector memory folded InstRW overrides.
We have test coverage for these with resources-sse*/avx*
Modified:
llvm/trunk/lib/Target/X86/X86SchedBroadwell.td
llvm/trunk/lib/Target/X86/X86SchedHaswell.td
llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td
llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td
Modified: llvm/trunk/lib/Target/X86/X86SchedBroadwell.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedBroadwell.td?rev=330662&r1=330661&r2=330662&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedBroadwell.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedBroadwell.td Mon Apr 23 15:45:04 2018
@@ -968,48 +968,6 @@ def: InstRW<[BWWriteResGroup60], (instre
"VCVTPS2PHYrr",
"VCVTTPD2DQYrr")>;
-def BWWriteResGroup61 : SchedWriteRes<[BWPort5,BWPort23]> {
- let Latency = 6;
- let NumMicroOps = 2;
- let ResourceCycles = [1,1];
-}
-def: InstRW<[BWWriteResGroup61], (instregex "(V?)INSERTPSrm",
- "(V?)MOVHPDrm",
- "(V?)MOVHPSrm",
- "(V?)MOVLPDrm",
- "(V?)MOVLPSrm",
- "(V?)PACKSSDWrm",
- "(V?)PACKSSWBrm",
- "(V?)PACKUSDWrm",
- "(V?)PACKUSWBrm",
- "(V?)PALIGNRrmi",
- "VPERMILPDmi",
- "VPERMILPDrm",
- "VPERMILPSmi",
- "VPERMILPSrm",
- "(V?)PINSRBrm",
- "(V?)PINSRDrm",
- "(V?)PINSRQrm",
- "(V?)PINSRWrm",
- "(V?)PSHUFBrm",
- "(V?)PSHUFDmi",
- "(V?)PSHUFHWmi",
- "(V?)PSHUFLWmi",
- "(V?)PUNPCKHBWrm",
- "(V?)PUNPCKHDQrm",
- "(V?)PUNPCKHQDQrm",
- "(V?)PUNPCKHWDrm",
- "(V?)PUNPCKLBWrm",
- "(V?)PUNPCKLDQrm",
- "(V?)PUNPCKLQDQrm",
- "(V?)PUNPCKLWDrm",
- "(V?)SHUFPDrmi",
- "(V?)SHUFPSrmi",
- "(V?)UNPCKHPDrm",
- "(V?)UNPCKHPSrm",
- "(V?)UNPCKLPDrm",
- "(V?)UNPCKLPSrm")>;
-
def BWWriteResGroup62 : SchedWriteRes<[BWPort6,BWPort23]> {
let Latency = 6;
let NumMicroOps = 2;
@@ -1038,50 +996,7 @@ def: InstRW<[BWWriteResGroup64], (instre
"BLSI(32|64)rm",
"BLSMSK(32|64)rm",
"BLSR(32|64)rm",
- "MOVBE(16|32|64)rm",
- "(V?)PABSBrm",
- "(V?)PABSDrm",
- "(V?)PABSWrm",
- "(V?)PADDBrm",
- "(V?)PADDDrm",
- "(V?)PADDQrm",
- "(V?)PADDSBrm",
- "(V?)PADDSWrm",
- "(V?)PADDUSBrm",
- "(V?)PADDUSWrm",
- "(V?)PADDWrm",
- "(V?)PAVGBrm",
- "(V?)PAVGWrm",
- "(V?)PCMPEQBrm",
- "(V?)PCMPEQDrm",
- "(V?)PCMPEQQrm",
- "(V?)PCMPEQWrm",
- "(V?)PCMPGTBrm",
- "(V?)PCMPGTDrm",
- "(V?)PCMPGTWrm",
- "(V?)PMAXSBrm",
- "(V?)PMAXSDrm",
- "(V?)PMAXSWrm",
- "(V?)PMAXUBrm",
- "(V?)PMAXUDrm",
- "(V?)PMAXUWrm",
- "(V?)PMINSBrm",
- "(V?)PMINSDrm",
- "(V?)PMINSWrm",
- "(V?)PMINUBrm",
- "(V?)PMINUDrm",
- "(V?)PMINUWrm",
- "(V?)PSIGNBrm",
- "(V?)PSIGNDrm",
- "(V?)PSIGNWrm",
- "(V?)PSUBBrm",
- "(V?)PSUBDrm",
- "(V?)PSUBQrm",
- "(V?)PSUBSBrm",
- "(V?)PSUBSWrm",
- "(V?)PSUBUSBrm",
- "(V?)PSUBUSWrm",
- "(V?)PSUBWrm")>;
+ "MOVBE(16|32|64)rm")>;
def BWWriteResGroup65 : SchedWriteRes<[BWPort23,BWPort015]> {
let Latency = 6;
@@ -1384,17 +1299,7 @@ def BWWriteResGroup91 : SchedWriteRes<[B
def: InstRW<[BWWriteResGroup91], (instregex "MMX_CVTPI2PSirm",
"PDEP(32|64)rm",
"PEXT(32|64)rm",
- "(V?)ADDPDrm",
- "(V?)ADDPSrm",
- "(V?)ADDSDrm",
- "(V?)ADDSSrm",
- "(V?)ADDSUBPDrm",
- "(V?)ADDSUBPSrm",
- "(V?)CVTDQ2PSrm",
- "(V?)SUBPDrm",
- "(V?)SUBPSrm",
- "(V?)SUBSDrm",
- "(V?)SUBSSrm")>;
+ "(V?)CVTDQ2PSrm")>;
def BWWriteResGroup91_16 : SchedWriteRes<[BWPort1, BWPort0156, BWPort23]> {
let Latency = 8;
@@ -1648,11 +1553,7 @@ def BWWriteResGroup115 : SchedWriteRes<[
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[BWWriteResGroup115], (instregex "(V?)PCMPGTQrm",
- "(V?)PHMINPOSUWrm",
- "(V?)PMADDUBSWrm",
- "(V?)PMADDWDrm",
- "(V?)PSADBWrm")>;
+def: InstRW<[BWWriteResGroup115], (instregex "(V?)PCMPGTQrm")>;
def BWWriteResGroup116 : SchedWriteRes<[BWPort01,BWPort23]> {
let Latency = 10;
Modified: llvm/trunk/lib/Target/X86/X86SchedHaswell.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedHaswell.td?rev=330662&r1=330661&r2=330662&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedHaswell.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedHaswell.td Mon Apr 23 15:45:04 2018
@@ -820,16 +820,12 @@ def: InstRW<[HWWriteResGroup12], (instre
"MMX_CVTPI2PSirm",
"PDEP(32|64)rm",
"PEXT(32|64)rm",
- "(V?)ADDSDrm",
- "(V?)ADDSSrm",
"(V?)CMPSDrm",
"(V?)CMPSSrm",
"(V?)MAX(C?)SDrm",
"(V?)MAX(C?)SSrm",
"(V?)MIN(C?)SDrm",
- "(V?)MIN(C?)SSrm",
- "(V?)SUBSDrm",
- "(V?)SUBSSrm")>;
+ "(V?)MIN(C?)SSrm")>;
def HWWriteResGroup12_1 : SchedWriteRes<[HWPort1,HWPort0156,HWPort23]> {
let Latency = 8;
@@ -925,20 +921,6 @@ def: InstRW<[HWWriteResGroup13_1], (inst
"VXORPDYrm",
"VXORPSYrm")>;
-def HWWriteResGroup13_2 : SchedWriteRes<[HWPort5,HWPort23]> {
- let Latency = 6;
- let NumMicroOps = 2;
- let ResourceCycles = [1,1];
-}
-def: InstRW<[HWWriteResGroup13_2], (instregex "(V?)MOVHPDrm",
- "(V?)MOVHPSrm",
- "(V?)MOVLPDrm",
- "(V?)MOVLPSrm",
- "(V?)PINSRBrm",
- "(V?)PINSRDrm",
- "(V?)PINSRQrm",
- "(V?)PINSRWrm")>;
-
def HWWriteResGroup14 : SchedWriteRes<[HWPort6,HWPort23]> {
let Latency = 6;
let NumMicroOps = 2;
@@ -1626,18 +1608,6 @@ def: InstRW<[HWWriteResGroup64_1], (inst
"VPHSUBSWYrm",
"VPHSUBWYrm")>;
-def HWWriteResGroup64_2 : SchedWriteRes<[HWPort5,HWPort23,HWPort15]> {
- let Latency = 9;
- let NumMicroOps = 4;
- let ResourceCycles = [2,1,1];
-}
-def: InstRW<[HWWriteResGroup64_2], (instregex "(V?)PHADDDrm",
- "(V?)PHADDSWrm",
- "(V?)PHADDWrm",
- "(V?)PHSUBDrm",
- "(V?)PHSUBSWrm",
- "(V?)PHSUBWrm")>;
-
def HWWriteResGroup65 : SchedWriteRes<[HWPort23,HWPort06,HWPort0156]> {
let Latency = 8;
let NumMicroOps = 4;
@@ -1909,14 +1879,6 @@ def: InstRW<[HWWriteResGroup90], (instre
"(V?)MULSDrr",
"(V?)MULSSrr")>;
-def HWWriteResGroup91 : SchedWriteRes<[HWPort0,HWPort23]> {
- let Latency = 10;
- let NumMicroOps = 2;
- let ResourceCycles = [1,1];
-}
-def: InstRW<[HWWriteResGroup91], (instregex "(V?)RCPSSm",
- "(V?)RSQRTSSm")>;
-
def HWWriteResGroup91_1 : SchedWriteRes<[HWPort0,HWPort23,HWFPDivider]> {
let Latency = 16;
let NumMicroOps = 2;
Modified: llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td?rev=330662&r1=330661&r2=330662&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td Mon Apr 23 15:45:04 2018
@@ -1140,20 +1140,6 @@ def: InstRW<[SKLWriteResGroup70], (instr
"(V?)CVTTSD2SI64rr",
"(V?)CVTTSD2SIrr")>;
-def SKLWriteResGroup71 : SchedWriteRes<[SKLPort5,SKLPort23]> {
- let Latency = 6;
- let NumMicroOps = 2;
- let ResourceCycles = [1,1];
-}
-def: InstRW<[SKLWriteResGroup71], (instregex "(V?)MOVHPDrm",
- "(V?)MOVHPSrm",
- "(V?)MOVLPDrm",
- "(V?)MOVLPSrm",
- "(V?)PINSRBrm",
- "(V?)PINSRDrm",
- "(V?)PINSRQrm",
- "(V?)PINSRWrm")>;
-
def SKLWriteResGroup72 : SchedWriteRes<[SKLPort6,SKLPort23]> {
let Latency = 6;
let NumMicroOps = 2;
@@ -1742,8 +1728,6 @@ def: InstRW<[SKLWriteResGroup120], (inst
"MMX_PMULHWirm",
"MMX_PMULLWirm",
"MMX_PMULUDQirm",
- "(V?)RCPSSm",
- "(V?)RSQRTSSm",
"VTESTPDYrm",
"VTESTPSYrm")>;
Modified: llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td?rev=330662&r1=330661&r2=330662&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td Mon Apr 23 15:45:04 2018
@@ -2287,36 +2287,6 @@ def: InstRW<[SKXWriteResGroup74], (instr
"VCVTTSD2USIZrr(b?)",
"VCVTTSS2USIZrr(b?)")>;
-def SKXWriteResGroup75 : SchedWriteRes<[SKXPort5,SKXPort23]> {
- let Latency = 6;
- let NumMicroOps = 2;
- let ResourceCycles = [1,1];
-}
-def: InstRW<[SKXWriteResGroup75], (instregex "MOVHPDrm",
- "MOVHPSrm",
- "MOVLPDrm",
- "MOVLPSrm",
- "PINSRBrm",
- "PINSRDrm",
- "PINSRQrm",
- "PINSRWrm",
- "VMOVHPDZ128rm(b?)",
- "VMOVHPDrm",
- "VMOVHPSZ128rm(b?)",
- "VMOVHPSrm",
- "VMOVLPDZ128rm(b?)",
- "VMOVLPDrm",
- "VMOVLPSZ128rm(b?)",
- "VMOVLPSrm",
- "VPINSRBZrm(b?)",
- "VPINSRBrm",
- "VPINSRDZrm(b?)",
- "VPINSRDrm",
- "VPINSRQZrm(b?)",
- "VPINSRQrm",
- "VPINSRWZrm(b?)",
- "VPINSRWrm")>;
-
def SKXWriteResGroup76 : SchedWriteRes<[SKXPort6,SKXPort23]> {
let Latency = 6;
let NumMicroOps = 2;
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