[llvm] r330611 - [X86] Replace x87 instregex with instrs if they only match one instruction
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Mon Apr 23 09:10:50 PDT 2018
Author: rksimon
Date: Mon Apr 23 09:10:50 2018
New Revision: 330611
URL: http://llvm.org/viewvc/llvm-project?rev=330611&view=rev
Log:
[X86] Replace x87 instregex with instrs if they only match one instruction
Modified:
llvm/trunk/lib/Target/X86/X86SchedBroadwell.td
llvm/trunk/lib/Target/X86/X86SchedHaswell.td
llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td
llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td
llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td
llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td
Modified: llvm/trunk/lib/Target/X86/X86SchedBroadwell.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedBroadwell.td?rev=330611&r1=330610&r2=330611&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedBroadwell.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedBroadwell.td Mon Apr 23 09:10:50 2018
@@ -368,8 +368,7 @@ def BWWriteResGroup5 : SchedWriteRes<[BW
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[BWWriteResGroup5], (instregex "FINCSTP",
- "FNOP")>;
+def: InstRW<[BWWriteResGroup5], (instrs FINCSTP, FNOP)>;
def BWWriteResGroup6 : SchedWriteRes<[BWPort06]> {
let Latency = 1;
@@ -480,7 +479,7 @@ def BWWriteResGroup12 : SchedWriteRes<[B
let NumMicroOps = 2;
let ResourceCycles = [2];
}
-def: InstRW<[BWWriteResGroup12], (instregex "FDECSTP")>;
+def: InstRW<[BWWriteResGroup12], (instrs FDECSTP)>;
def BWWriteResGroup13 : SchedWriteRes<[BWPort06]> {
let Latency = 2;
@@ -824,7 +823,7 @@ def BWWriteResGroup45 : SchedWriteRes<[B
let NumMicroOps = 4;
let ResourceCycles = [4];
}
-def: InstRW<[BWWriteResGroup45], (instregex "FNCLEX")>;
+def: InstRW<[BWWriteResGroup45], (instrs FNCLEX)>;
def BWWriteResGroup46 : SchedWriteRes<[BWPort015,BWPort0156]> {
let Latency = 4;
@@ -2275,7 +2274,7 @@ def BWWriteResGroup200 : SchedWriteRes<[
let NumMicroOps = 15;
let ResourceCycles = [6,3,6];
}
-def: InstRW<[BWWriteResGroup200], (instregex "FNINIT")>;
+def: InstRW<[BWWriteResGroup200], (instrs FNINIT)>;
def BWWriteResGroup201 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort6,BWPort01,BWPort0156]> {
let Latency = 80;
Modified: llvm/trunk/lib/Target/X86/X86SchedHaswell.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedHaswell.td?rev=330611&r1=330610&r2=330611&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedHaswell.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedHaswell.td Mon Apr 23 09:10:50 2018
@@ -513,7 +513,7 @@ def : InstRW<[HWWrite3P01], (instregex "
def : InstRW<[HWWriteP1], (instregex "TST_F")>;
// FXAM.
-def : InstRW<[HWWrite2P1], (instregex "FXAM")>;
+def : InstRW<[HWWrite2P1], (instrs FXAM)>;
// FPREM.
def HWWriteFPREM : SchedWriteRes<[]> {
@@ -534,7 +534,7 @@ def HWWriteFRNDINT : SchedWriteRes<[]> {
let Latency = 11;
let NumMicroOps = 17;
}
-def : InstRW<[HWWriteFRNDINT], (instregex "FRNDINT")>;
+def : InstRW<[HWWriteFRNDINT], (instrs FRNDINT)>;
//-- Math instructions --//
@@ -543,14 +543,14 @@ def HWWriteFSCALE : SchedWriteRes<[]> {
let Latency = 75; // 49-125
let NumMicroOps = 50; // 25-75
}
-def : InstRW<[HWWriteFSCALE], (instregex "FSCALE")>;
+def : InstRW<[HWWriteFSCALE], (instrs FSCALE)>;
// FXTRACT.
def HWWriteFXTRACT : SchedWriteRes<[]> {
let Latency = 15;
let NumMicroOps = 17;
}
-def : InstRW<[HWWriteFXTRACT], (instregex "FXTRACT")>;
+def : InstRW<[HWWriteFXTRACT], (instrs FXTRACT)>;
////////////////////////////////////////////////////////////////////////////////
// Horizontal add/sub instructions.
@@ -710,8 +710,7 @@ def HWWriteResGroup6 : SchedWriteRes<[HW
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[HWWriteResGroup6], (instregex "FINCSTP",
- "FNOP")>;
+def: InstRW<[HWWriteResGroup6], (instrs FINCSTP, FNOP)>;
def HWWriteResGroup7 : SchedWriteRes<[HWPort06]> {
let Latency = 1;
@@ -1204,7 +1203,7 @@ def HWWriteResGroup28 : SchedWriteRes<[H
let NumMicroOps = 2;
let ResourceCycles = [2];
}
-def: InstRW<[HWWriteResGroup28], (instregex "FDECSTP")>;
+def: InstRW<[HWWriteResGroup28], (instrs FDECSTP)>;
def HWWriteResGroup29 : SchedWriteRes<[HWPort06]> {
let Latency = 2;
@@ -1223,7 +1222,7 @@ def HWWriteResGroup30 : SchedWriteRes<[H
}
def: InstRW<[HWWriteResGroup30], (instregex "LFENCE")>;
def: InstRW<[HWWriteResGroup30], (instregex "MFENCE")>;
-def: InstRW<[HWWriteResGroup30], (instregex "WAIT")>;
+def: InstRW<[HWWriteResGroup30], (instrs WAIT)>;
def: InstRW<[HWWriteResGroup30], (instregex "XGETBV")>;
def HWWriteResGroup31 : SchedWriteRes<[HWPort0,HWPort5]> {
@@ -1845,7 +1844,7 @@ def HWWriteResGroup81 : SchedWriteRes<[H
let NumMicroOps = 4;
let ResourceCycles = [4];
}
-def: InstRW<[HWWriteResGroup81], (instregex "FNCLEX")>;
+def: InstRW<[HWWriteResGroup81], (instrs FNCLEX)>;
def HWWriteResGroup82 : SchedWriteRes<[HWPort015,HWPort0156]> {
let Latency = 4;
@@ -2572,7 +2571,7 @@ def HWWriteResGroup180 : SchedWriteRes<[
let NumMicroOps = 15;
let ResourceCycles = [6,3,6];
}
-def: InstRW<[HWWriteResGroup180], (instregex "FNINIT")>;
+def: InstRW<[HWWriteResGroup180], (instrs FNINIT)>;
def HWWriteResGroup181 : SchedWriteRes<[HWPort0,HWPort1,HWPort5,HWPort6,HWPort01,HWPort0156]> {
let Latency = 98;
Modified: llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td?rev=330611&r1=330610&r2=330611&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td Mon Apr 23 09:10:50 2018
@@ -328,11 +328,9 @@ def SBWriteResGroup2 : SchedWriteRes<[SB
let NumMicroOps = 1;
let ResourceCycles = [1];
}
+def: InstRW<[SBWriteResGroup2], (instrs FDECSTP, FINCSTP, FNOP)>;
def: InstRW<[SBWriteResGroup2], (instrs LOOP, LOOPE, LOOPNE)>; // FIXME: This seems wrong compared to other Intel CPUs.
-def: InstRW<[SBWriteResGroup2], (instregex "FDECSTP",
- "FFREE",
- "FINCSTP",
- "FNOP",
+def: InstRW<[SBWriteResGroup2], (instregex "FFREE",
"LD_Frr",
"RETQ",
"ST_FPrr",
@@ -826,7 +824,7 @@ def SBWriteResGroup41 : SchedWriteRes<[S
let NumMicroOps = 4;
let ResourceCycles = [1,3];
}
-def: InstRW<[SBWriteResGroup41], (instregex "FNINIT")>;
+def: InstRW<[SBWriteResGroup41], (instrs FNINIT)>;
def SBWriteResGroup42 : SchedWriteRes<[SBPort05,SBPort015]> {
let Latency = 5;
Modified: llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td?rev=330611&r1=330610&r2=330611&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td Mon Apr 23 09:10:50 2018
@@ -433,9 +433,8 @@ def SKLWriteResGroup6 : SchedWriteRes<[S
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[SKLWriteResGroup6], (instregex "FINCSTP",
- "FNOP",
- "MMX_MOVQ64rr",
+def: InstRW<[SKLWriteResGroup6], (instrs FINCSTP, FNOP)>;
+def: InstRW<[SKLWriteResGroup6], (instregex "MMX_MOVQ64rr",
"MMX_PABS(B|D|W)rr",
"MMX_PADD(B|D|Q|W)irr",
"MMX_PANDNirr",
@@ -589,8 +588,8 @@ def SKLWriteResGroup14 : SchedWriteRes<[
let NumMicroOps = 2;
let ResourceCycles = [2];
}
-def: InstRW<[SKLWriteResGroup14], (instregex "FDECSTP",
- "MMX_MOVDQ2Qrr")>;
+def: InstRW<[SKLWriteResGroup14], (instrs FDECSTP)>;
+def: InstRW<[SKLWriteResGroup14], (instregex "MMX_MOVDQ2Qrr")>;
def SKLWriteResGroup15 : SchedWriteRes<[SKLPort06]> {
let Latency = 2;
@@ -990,7 +989,7 @@ def SKLWriteResGroup54 : SchedWriteRes<[
let NumMicroOps = 4;
let ResourceCycles = [4];
}
-def: InstRW<[SKLWriteResGroup54], (instregex "FNCLEX")>;
+def: InstRW<[SKLWriteResGroup54], (instrs FNCLEX)>;
def SKLWriteResGroup55 : SchedWriteRes<[SKLPort6,SKLPort0156]> {
let Latency = 4;
@@ -2581,7 +2580,7 @@ def SKLWriteResGroup220 : SchedWriteRes<
let NumMicroOps = 15;
let ResourceCycles = [6,3,6];
}
-def: InstRW<[SKLWriteResGroup220], (instregex "FNINIT")>;
+def: InstRW<[SKLWriteResGroup220], (instrs FNINIT)>;
def SKLWriteResGroup221 : SchedWriteRes<[SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort05,SKLPort0156]> {
let Latency = 76;
Modified: llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td?rev=330611&r1=330610&r2=330611&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td Mon Apr 23 09:10:50 2018
@@ -738,9 +738,8 @@ def SKXWriteResGroup6 : SchedWriteRes<[S
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[SKXWriteResGroup6], (instregex "FINCSTP",
- "FNOP",
- "MMX_MOVQ64rr",
+def: InstRW<[SKXWriteResGroup6], (instrs FINCSTP, FNOP)>;
+def: InstRW<[SKXWriteResGroup6], (instregex "MMX_MOVQ64rr",
"MMX_PABS(B|D|W)rr",
"MMX_PADD(B|D|Q|W)irr",
"MMX_PANDNirr",
@@ -1061,8 +1060,8 @@ def SKXWriteResGroup14 : SchedWriteRes<[
let NumMicroOps = 2;
let ResourceCycles = [2];
}
-def: InstRW<[SKXWriteResGroup14], (instregex "FDECSTP",
- "MMX_MOVDQ2Qrr")>;
+def: InstRW<[SKXWriteResGroup14], (instrs FDECSTP)>;
+def: InstRW<[SKXWriteResGroup14], (instregex "MMX_MOVDQ2Qrr")>;
def SKXWriteResGroup15 : SchedWriteRes<[SKXPort06]> {
let Latency = 2;
@@ -1981,7 +1980,7 @@ def SKXWriteResGroup55 : SchedWriteRes<[
let NumMicroOps = 4;
let ResourceCycles = [4];
}
-def: InstRW<[SKXWriteResGroup55], (instregex "FNCLEX")>;
+def: InstRW<[SKXWriteResGroup55], (instrs FNCLEX)>;
def SKXWriteResGroup56 : SchedWriteRes<[SKXPort015,SKXPort0156]> {
let Latency = 4;
@@ -5168,7 +5167,7 @@ def SKXWriteResGroup263 : SchedWriteRes<
let NumMicroOps = 15;
let ResourceCycles = [6,3,6];
}
-def: InstRW<[SKXWriteResGroup263], (instregex "FNINIT")>;
+def: InstRW<[SKXWriteResGroup263], (instrs FNINIT)>;
def SKXWriteResGroup264 : SchedWriteRes<[SKXPort0,SKXPort1,SKXPort5,SKXPort6,SKXPort05,SKXPort0156]> {
let Latency = 76;
Modified: llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td?rev=330611&r1=330610&r2=330611&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td (original)
+++ llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td Mon Apr 23 09:10:50 2018
@@ -763,7 +763,7 @@ def : InstRW<[WriteMicrocoded], (instreg
def : InstRW<[WriteMicrocoded], (instregex "FNSTCW16m")>;
// FINCSTP FDECSTP.
-def : InstRW<[ZnWriteFPU3], (instregex "FINCSTP", "FDECSTP")>;
+def : InstRW<[ZnWriteFPU3], (instrs FINCSTP, FDECSTP)>;
// FFREE.
def : InstRW<[ZnWriteFPU3], (instregex "FFREE")>;
@@ -822,7 +822,7 @@ def : InstRW<[ZnWriteFPU03], (instregex
def : InstRW<[ZnWriteFPU0Lat1], (instregex "TST_F")>;
// FXAM.
-def : InstRW<[ZnWriteFPU3Lat1], (instregex "FXAM")>;
+def : InstRW<[ZnWriteFPU3Lat1], (instrs FXAM)>;
// FPREM.
def : InstRW<[WriteMicrocoded], (instrs FPREM)>;
@@ -831,25 +831,25 @@ def : InstRW<[WriteMicrocoded], (instrs
def : InstRW<[WriteMicrocoded], (instrs FPREM1)>;
// FRNDINT.
-def : InstRW<[WriteMicrocoded], (instregex "FRNDINT")>;
+def : InstRW<[WriteMicrocoded], (instrs FRNDINT)>;
// FSCALE.
-def : InstRW<[WriteMicrocoded], (instregex "FSCALE")>;
+def : InstRW<[WriteMicrocoded], (instrs FSCALE)>;
// FXTRACT.
-def : InstRW<[WriteMicrocoded], (instregex "FXTRACT")>;
+def : InstRW<[WriteMicrocoded], (instrs FXTRACT)>;
// FNOP.
-def : InstRW<[ZnWriteFPU0Lat1], (instregex "FNOP")>;
+def : InstRW<[ZnWriteFPU0Lat1], (instrs FNOP)>;
// WAIT.
-def : InstRW<[ZnWriteFPU0Lat1], (instregex "WAIT")>;
+def : InstRW<[ZnWriteFPU0Lat1], (instrs WAIT)>;
// FNCLEX.
-def : InstRW<[WriteMicrocoded], (instregex "FNCLEX")>;
+def : InstRW<[WriteMicrocoded], (instrs FNCLEX)>;
// FNINIT.
-def : InstRW<[WriteMicrocoded], (instregex "FNINIT")>;
+def : InstRW<[WriteMicrocoded], (instrs FNINIT)>;
//=== Integer MMX and XMM Instructions ===//
//-- Move instructions --//
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