[llvm] r330545 - [X86][MMX][SSE] Tag missed PHADD/PHSUB instructions with WritePHAdd
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Sun Apr 22 08:02:23 PDT 2018
Author: rksimon
Date: Sun Apr 22 08:02:23 2018
New Revision: 330545
URL: http://llvm.org/viewvc/llvm-project?rev=330545&view=rev
Log:
[X86][MMX][SSE] Tag missed PHADD/PHSUB instructions with WritePHAdd
Modified:
llvm/trunk/lib/Target/X86/X86InstrMMX.td
llvm/trunk/lib/Target/X86/X86InstrSSE.td
llvm/trunk/test/CodeGen/X86/avx2-schedule.ll
Modified: llvm/trunk/lib/Target/X86/X86InstrMMX.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrMMX.td?rev=330545&r1=330544&r2=330545&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrMMX.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrMMX.td Sun Apr 22 08:02:23 2018
@@ -339,11 +339,11 @@ defm MMX_PSUBUSW : MMXI_binop_rm_int<0xD
WriteVecALU>;
defm MMX_PHSUBW : SS3I_binop_rm_int_mm<0x05, "phsubw", int_x86_ssse3_phsub_w,
- WriteVecALU>;
+ WritePHAdd>;
defm MMX_PHSUBD : SS3I_binop_rm_int_mm<0x06, "phsubd", int_x86_ssse3_phsub_d,
- WriteVecALU>;
+ WritePHAdd>;
defm MMX_PHSUBSW : SS3I_binop_rm_int_mm<0x07, "phsubsw",int_x86_ssse3_phsub_sw,
- WriteVecALU>;
+ WritePHAdd>;
// -- Multiplication
defm MMX_PMULLW : MMXI_binop_rm_int<0xD5, "pmullw", int_x86_mmx_pmull_w,
Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=330545&r1=330544&r2=330545&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Sun Apr 22 08:02:23 2018
@@ -4710,10 +4710,10 @@ let isCommutable = 0 in {
WriteVecALU>, VEX_4V, VEX_L, VEX_WIG;
defm VPHADDSW : SS3I_binop_rm_int_y<0x03, "vphaddsw",
int_x86_avx2_phadd_sw,
- WriteVecALU>, VEX_4V, VEX_L, VEX_WIG;
+ WritePHAdd>, VEX_4V, VEX_L, VEX_WIG;
defm VPHSUBSW : SS3I_binop_rm_int_y<0x07, "vphsubsw",
int_x86_avx2_phsub_sw,
- WriteVecALU>, VEX_4V, VEX_L, VEX_WIG;
+ WritePHAdd>, VEX_4V, VEX_L, VEX_WIG;
}
}
Modified: llvm/trunk/test/CodeGen/X86/avx2-schedule.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx2-schedule.ll?rev=330545&r1=330544&r2=330545&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx2-schedule.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx2-schedule.ll Sun Apr 22 08:02:23 2018
@@ -3081,8 +3081,8 @@ declare <8 x i32> @llvm.x86.avx2.phadd.d
define <16 x i16> @test_phaddsw(<16 x i16> %a0, <16 x i16> %a1, <16 x i16> *%a2) {
; GENERIC-LABEL: test_phaddsw:
; GENERIC: # %bb.0:
-; GENERIC-NEXT: vphaddsw %ymm1, %ymm0, %ymm0 # sched: [3:1.00]
-; GENERIC-NEXT: vphaddsw (%rdi), %ymm0, %ymm0 # sched: [8:1.00]
+; GENERIC-NEXT: vphaddsw %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
+; GENERIC-NEXT: vphaddsw (%rdi), %ymm0, %ymm0 # sched: [6:0.50]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; HASWELL-LABEL: test_phaddsw:
@@ -3210,8 +3210,8 @@ declare <8 x i32> @llvm.x86.avx2.phsub.d
define <16 x i16> @test_phsubsw(<16 x i16> %a0, <16 x i16> %a1, <16 x i16> *%a2) {
; GENERIC-LABEL: test_phsubsw:
; GENERIC: # %bb.0:
-; GENERIC-NEXT: vphsubsw %ymm1, %ymm0, %ymm0 # sched: [3:1.00]
-; GENERIC-NEXT: vphsubsw (%rdi), %ymm0, %ymm0 # sched: [8:1.00]
+; GENERIC-NEXT: vphsubsw %ymm1, %ymm0, %ymm0 # sched: [1:0.50]
+; GENERIC-NEXT: vphsubsw (%rdi), %ymm0, %ymm0 # sched: [6:0.50]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; HASWELL-LABEL: test_phsubsw:
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