[llvm] r330541 - [X86][SandyBridge] Remove unnecessary WritePOPCNTLd overrides by fixing load latency.

[Simon Pilgrim via llvm-commits]

Author: rksimon
Date: Sun Apr 22 03:03:52 2018
New Revision: 330541

URL: http://llvm.org/viewvc/llvm-project?rev=330541&view=rev
Log:
[X86][SandyBridge] Remove unnecessary WritePOPCNTLd overrides by fixing load latency.

Modified:
    llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td

Modified: llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td?rev=330541&r1=330540&r2=330541&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td Sun Apr 22 03:03:52 2018
@@ -126,7 +126,7 @@ def : WriteRes<WriteLEA, [SBPort15]>;
 defm : SBWriteResPair<WriteBitScan, [SBPort1], 3, [1], 1, 5>;
 defm : SBWriteResPair<WriteLZCNT,   [SBPort1], 3, [1], 1, 5>;
 defm : SBWriteResPair<WriteTZCNT,   [SBPort1], 3, [1], 1, 5>;
-defm : SBWriteResPair<WritePOPCNT,  [SBPort1], 3, [1], 1, 5>;
+defm : SBWriteResPair<WritePOPCNT,  [SBPort1], 3, [1], 1, 6>;
 
 // BMI1 BEXTR, BMI2 BZHI
 // NOTE: These don't exist on Sandy Bridge. Ports are guesses.
@@ -1392,7 +1392,6 @@ def SBWriteResGroup90 : SchedWriteRes<[S
 }
 def: InstRW<[SBWriteResGroup90], (instregex "MMX_CVTPS2PIirm",
                                             "MMX_CVTTPS2PIirm",
-                                            "POPCNT(16|32|64)rm",
                                             "(V?)ADDPDrm",
                                             "(V?)ADDPSrm",
                                             "(V?)ADDSDrm",