[llvm] r330533 - [X86] Change TB to PS on LFENCE instruction.

[Craig Topper via llvm-commits]

Author: ctopper
Date: Sat Apr 21 20:15:02 2018
New Revision: 330533

URL: http://llvm.org/viewvc/llvm-project?rev=330533&view=rev
Log:
[X86] Change TB to PS on LFENCE instruction.

This matches the other FENCE instructions.

Modified:
    llvm/trunk/lib/Target/X86/X86InstrSSE.td

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=330533&r1=330532&r2=330533&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Sat Apr 21 20:15:02 2018
@@ -3104,7 +3104,7 @@ let SchedRW = [WriteFence] in {
 def SFENCE : I<0xAE, MRM_F8, (outs), (ins), "sfence", [(int_x86_sse_sfence)]>,
                PS, Requires<[HasSSE1]>;
 def LFENCE : I<0xAE, MRM_E8, (outs), (ins), "lfence", [(int_x86_sse2_lfence)]>,
-               TB, Requires<[HasSSE2]>;
+               PS, Requires<[HasSSE2]>;
 def MFENCE : I<0xAE, MRM_F0, (outs), (ins), "mfence", [(int_x86_sse2_mfence)]>,
                PS, Requires<[HasMFence]>;
 } // SchedRW