[llvm] r330527 - [X86] Strip unnecessary prefetch + vector move/load instrw overrides from scheduler models.
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Sat Apr 21 14:59:36 PDT 2018
Author: rksimon
Date: Sat Apr 21 14:59:36 2018
New Revision: 330527
URL: http://llvm.org/viewvc/llvm-project?rev=330527&view=rev
Log:
[X86] Strip unnecessary prefetch + vector move/load instrw overrides from scheduler models.
Modified:
llvm/trunk/lib/Target/X86/X86SchedBroadwell.td
llvm/trunk/lib/Target/X86/X86SchedHaswell.td
llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td
llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td
llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td
Modified: llvm/trunk/lib/Target/X86/X86SchedBroadwell.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedBroadwell.td?rev=330527&r1=330526&r2=330527&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedBroadwell.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedBroadwell.td Sat Apr 21 14:59:36 2018
@@ -352,11 +352,7 @@ def: InstRW<[BWWriteResGroup3], (instreg
"MMX_MOVD64to64rr",
"MMX_MOVQ2DQrr",
"(V?)MOV64toPQIrr",
- "(V?)MOVAPD(Y?)rr",
- "(V?)MOVAPS(Y?)rr",
"(V?)MOVDI2PDIrr",
- "(V?)MOVUPD(Y?)rr",
- "(V?)MOVUPS(Y?)rr",
"(V?)PBLENDW(Y?)rri",
"(V?)PSLLDQ(Y?)ri",
"(V?)PSRLDQ(Y?)ri")>;
@@ -416,10 +412,6 @@ def BWWriteResGroup8 : SchedWriteRes<[BW
let ResourceCycles = [1];
}
def: InstRW<[BWWriteResGroup8], (instregex "MMX_MOVQ64rr",
- "(V?)MOVDQA(Y?)rr",
- "(V?)MOVDQU(Y?)rr",
- "(V?)MOVPQI2QIrr",
- "VMOVZPQILo2PQIrr",
"VPBLENDD(Y?)rri")>;
def BWWriteResGroup9 : SchedWriteRes<[BWPort0156]> {
@@ -878,27 +870,10 @@ def: InstRW<[BWWriteResGroup49], (instre
"MOVSX(16|32|64)rm8",
"MOVZX(16|32|64)rm16",
"MOVZX(16|32|64)rm8",
- "PREFETCHNTA",
- "PREFETCHT0",
- "PREFETCHT1",
- "PREFETCHT2",
"VBROADCASTSSrm",
- "(V?)LDDQUrm",
- "(V?)MOV64toPQIrm",
- "(V?)MOVAPDrm",
- "(V?)MOVAPSrm",
"(V?)MOVDDUPrm",
- "(V?)MOVDI2PDIrm",
- "(V?)MOVDQArm",
- "(V?)MOVDQUrm",
- "(V?)MOVNTDQArm",
- "(V?)MOVQI2PQIrm",
- "(V?)MOVSDrm",
"(V?)MOVSHDUPrm",
"(V?)MOVSLDUPrm",
- "(V?)MOVSSrm",
- "(V?)MOVUPDrm",
- "(V?)MOVUPSrm",
"VPBROADCASTDrm",
"VPBROADCASTQrm")>;
Modified: llvm/trunk/lib/Target/X86/X86SchedHaswell.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedHaswell.td?rev=330527&r1=330526&r2=330527&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedHaswell.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedHaswell.td Sat Apr 21 14:59:36 2018
@@ -622,16 +622,7 @@ def: InstRW<[HWWriteResGroup0_2], (instr
"MOVSX(16|32|64)rm8",
"MOVZX(16|32|64)rm16",
"MOVZX(16|32|64)rm8",
- "PREFETCHNTA",
- "PREFETCHT0",
- "PREFETCHT1",
- "PREFETCHT2",
- "(V?)MOV64toPQIrm",
- "(V?)MOVDDUPrm",
- "(V?)MOVDI2PDIrm",
- "(V?)MOVQI2PQIrm",
- "(V?)MOVSDrm",
- "(V?)MOVSSrm")>;
+ "(V?)MOVDDUPrm")>;
def HWWriteResGroup1 : SchedWriteRes<[HWPort4,HWPort237]> {
let Latency = 1;
@@ -703,11 +694,7 @@ def: InstRW<[HWWriteResGroup4], (instreg
"MMX_MOVD64to64rr",
"MMX_MOVQ2DQrr",
"(V?)MOV64toPQIrr",
- "(V?)MOVAPD(Y?)rr",
- "(V?)MOVAPS(Y?)rr",
"(V?)MOVDI2PDIrr",
- "(V?)MOVUPD(Y?)rr",
- "(V?)MOVUPS(Y?)rr",
"(V?)PBLENDW(Y?)rri",
"(V?)PSLLDQ(Y?)ri",
"(V?)PSRLDQ(Y?)ri")>;
@@ -769,10 +756,6 @@ def HWWriteResGroup9 : SchedWriteRes<[HW
let ResourceCycles = [1];
}
def: InstRW<[HWWriteResGroup9], (instregex "MMX_MOVQ64rr",
- "(V?)MOVDQA(Y?)rr",
- "(V?)MOVDQU(Y?)rr",
- "(V?)MOVPQI2QIrr",
- "VMOVZPQILo2PQIrr",
"VPBLENDD(Y?)rri")>;
def HWWriteResGroup10 : SchedWriteRes<[HWPort0156]> {
Modified: llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td?rev=330527&r1=330526&r2=330527&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td Sat Apr 21 14:59:36 2018
@@ -497,15 +497,7 @@ def SKLWriteResGroup9 : SchedWriteRes<[S
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[SKLWriteResGroup9], (instregex "(V?)MOVAPD(Y?)rr",
- "(V?)MOVAPS(Y?)rr",
- "(V?)MOVDQA(Y?)rr",
- "(V?)MOVDQU(Y?)rr",
- "(V?)MOVPQI2QIrr",
- "(V?)MOVUPD(Y?)rr",
- "(V?)MOVUPS(Y?)rr",
- "(V?)MOVZPQILo2PQIrr",
- "(V?)PADDB(Y?)rr",
+def: InstRW<[SKLWriteResGroup9], (instregex "(V?)PADDB(Y?)rr",
"(V?)PADDD(Y?)rr",
"(V?)PADDQ(Y?)rr",
"(V?)PADDW(Y?)rr",
@@ -1053,16 +1045,7 @@ def: InstRW<[SKLWriteResGroup58], (instr
"MOVSX(16|32|64)rm8",
"MOVZX(16|32|64)rm16",
"MOVZX(16|32|64)rm8",
- "PREFETCHNTA",
- "PREFETCHT0",
- "PREFETCHT1",
- "PREFETCHT2",
- "(V?)MOV64toPQIrm",
- "(V?)MOVDDUPrm",
- "(V?)MOVDI2PDIrm",
- "(V?)MOVQI2PQIrm",
- "(V?)MOVSDrm",
- "(V?)MOVSSrm")>;
+ "(V?)MOVDDUPrm")>; // TODO: Should this be SKLWriteResGroup67?
def SKLWriteResGroup59 : SchedWriteRes<[SKLPort0,SKLPort5]> {
let Latency = 5;
@@ -1135,16 +1118,8 @@ def SKLWriteResGroup67 : SchedWriteRes<[
let ResourceCycles = [1];
}
def: InstRW<[SKLWriteResGroup67], (instregex "VBROADCASTSSrm",
- "(V?)LDDQUrm",
- "(V?)MOVAPDrm",
- "(V?)MOVAPSrm",
- "(V?)MOVDQArm",
- "(V?)MOVDQUrm",
- "(V?)MOVNTDQArm",
"(V?)MOVSHDUPrm",
"(V?)MOVSLDUPrm",
- "(V?)MOVUPDrm",
- "(V?)MOVUPSrm",
"VPBROADCASTDrm",
"VPBROADCASTQrm")>;
Modified: llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td?rev=330527&r1=330526&r2=330527&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td Sat Apr 21 14:59:36 2018
@@ -804,14 +804,7 @@ def SKXWriteResGroup9 : SchedWriteRes<[S
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[SKXWriteResGroup9], (instregex "MOVAPDrr",
- "MOVAPSrr",
- "MOVDQArr",
- "MOVDQUrr",
- "MOVPQI2QIrr",
- "MOVUPDrr",
- "MOVUPSrr",
- "PADDBrr",
+def: InstRW<[SKXWriteResGroup9], (instregex "PADDBrr",
"PADDDrr",
"PADDQrr",
"PADDWrr",
@@ -825,51 +818,6 @@ def: InstRW<[SKXWriteResGroup9], (instre
"VBLENDMPSZ128rr",
"VBLENDMPSZ256rr",
"VBLENDMPSZrr",
- "VMOVAPDYrr",
- "VMOVAPDZ128rr",
- "VMOVAPDZ256rr",
- "VMOVAPDZrr",
- "VMOVAPDrr",
- "VMOVAPSYrr",
- "VMOVAPSZ128rr",
- "VMOVAPSZ256rr",
- "VMOVAPSZrr",
- "VMOVAPSrr",
- "VMOVDQA32Z128rr",
- "VMOVDQA32Z256rr",
- "VMOVDQA32Zrr",
- "VMOVDQA64Z128rr",
- "VMOVDQA64Z256rr",
- "VMOVDQA64Zrr",
- "VMOVDQAYrr",
- "VMOVDQArr",
- "VMOVDQU16Z128rr",
- "VMOVDQU16Z256rr",
- "VMOVDQU16Zrr",
- "VMOVDQU32Z128rr",
- "VMOVDQU32Z256rr",
- "VMOVDQU32Zrr",
- "VMOVDQU64Z128rr",
- "VMOVDQU64Z256rr",
- "VMOVDQU64Zrr",
- "VMOVDQU8Z128rr",
- "VMOVDQU8Z256rr",
- "VMOVDQU8Zrr",
- "VMOVDQUYrr",
- "VMOVDQUrr",
- "VMOVPQI(2Q|Lo2PQ)IZrr",
- "VMOVPQI2QIrr",
- "VMOVUPDYrr",
- "VMOVUPDZ128rr",
- "VMOVUPDZ256rr",
- "VMOVUPDZrr",
- "VMOVUPDrr",
- "VMOVUPSZ128rr",
- "VMOVUPSZ256rr",
- "VMOVUPSZrr",
- "VMOVUPSYrr",
- "VMOVUPSrr",
- "VMOVZPQILo2PQIrr",
"VPADDBYrr",
"VPADDBZ128rr",
"VPADDBZ256rr",
@@ -2077,27 +2025,12 @@ def SKXWriteResGroup58 : SchedWriteRes<[
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[SKXWriteResGroup58], (instregex "MOV64toPQIrm",
- "MOVDDUPrm",
- "MOVDI2PDIrm",
- "MOVQI2PQIrm",
- "MOVSDrm",
- "MOVSSrm",
- "MOVSX(16|32|64)rm16",
+def: InstRW<[SKXWriteResGroup58], (instregex "MOVSX(16|32|64)rm16",
"MOVSX(16|32|64)rm32",
"MOVSX(16|32|64)rm8",
"MOVZX(16|32|64)rm16",
"MOVZX(16|32|64)rm8",
- "PREFETCHNTA",
- "PREFETCHT0",
- "PREFETCHT1",
- "PREFETCHT2",
- "VMOV64toPQIrm",
- "VMOVDDUPrm",
- "VMOVDI2PDIrm",
- "VMOVQI2PQIrm",
- "VMOVSDrm",
- "VMOVSSrm")>;
+ "(V?)MOVDDUPrm")>; // TODO: Should this be SKXWriteResGroup71?
def SKXWriteResGroup59 : SchedWriteRes<[SKXPort015]> {
let Latency = 5;
Modified: llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td?rev=330527&r1=330526&r2=330527&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td (original)
+++ llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td Sat Apr 21 14:59:36 2018
@@ -896,9 +896,6 @@ def : InstRW<[ZnWriteFPU2], (instregex "
def : InstRW<[ZnWriteFPU], (instregex "MMX_MOVQ64rr")>;
// (V)MOVDQA/U.
-// x <- x.
-def : InstRW<[ZnWriteFPU], (instregex "MOVDQ(A|U)rr", "VMOVDQ(A|U)rr")>;
-
// y <- y.
def : InstRW<[ZnWriteFPUY], (instregex "VMOVDQ(A|U)Yrr")>;
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