[llvm] r330510 - [X86] Strip unnecessary WriteFRcp/WriteFRsqrt instruction instrw overrides from scheduler models.
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Sat Apr 21 08:16:59 PDT 2018
Author: rksimon
Date: Sat Apr 21 08:16:59 2018
New Revision: 330510
URL: http://llvm.org/viewvc/llvm-project?rev=330510&view=rev
Log:
[X86] Strip unnecessary WriteFRcp/WriteFRsqrt instruction instrw overrides from scheduler models.
The required the default skylake schedules to be updated - these were being completely overriden by the InstRW and the existing values not used at all.
Modified:
llvm/trunk/lib/Target/X86/X86SchedBroadwell.td
llvm/trunk/lib/Target/X86/X86SchedHaswell.td
llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td
llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td
Modified: llvm/trunk/lib/Target/X86/X86SchedBroadwell.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedBroadwell.td?rev=330510&r1=330509&r2=330510&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedBroadwell.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedBroadwell.td Sat Apr 21 08:16:59 2018
@@ -966,11 +966,7 @@ def: InstRW<[BWWriteResGroup47], (instre
"(V?)PMULHUW(Y?)rr",
"(V?)PMULHW(Y?)rr",
"(V?)PMULLW(Y?)rr",
- "(V?)PMULUDQ(Y?)rr",
- "(V?)RCPPSr",
- "(V?)RCPSSr",
- "(V?)RSQRTPSr",
- "(V?)RSQRTSSr")>;
+ "(V?)PMULUDQ(Y?)rr")>;
def BWWriteResGroup49 : SchedWriteRes<[BWPort23]> {
let Latency = 5;
Modified: llvm/trunk/lib/Target/X86/X86SchedHaswell.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedHaswell.td?rev=330510&r1=330509&r2=330510&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedHaswell.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedHaswell.td Sat Apr 21 08:16:59 2018
@@ -2116,11 +2116,7 @@ def: InstRW<[HWWriteResGroup89], (instre
"(V?)PMULHUW(Y?)rr",
"(V?)PMULHW(Y?)rr",
"(V?)PMULLW(Y?)rr",
- "(V?)PMULUDQ(Y?)rr",
- "(V?)RCPPSr",
- "(V?)RCPSSr",
- "(V?)RSQRTPSr",
- "(V?)RSQRTSSr")>;
+ "(V?)PMULUDQ(Y?)rr")>;
def HWWriteResGroup90 : SchedWriteRes<[HWPort01]> {
let Latency = 5;
Modified: llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td?rev=330510&r1=330509&r2=330510&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td Sat Apr 21 08:16:59 2018
@@ -157,8 +157,8 @@ defm : SKLWriteResPair<WriteFCom, [SKL
defm : SKLWriteResPair<WriteFMul, [SKLPort0], 5>; // Floating point multiplication.
defm : SKLWriteResPair<WriteFDiv, [SKLPort0], 12>; // 10-14 cycles. // Floating point division.
defm : SKLWriteResPair<WriteFSqrt, [SKLPort0], 15>; // Floating point square root.
-defm : SKLWriteResPair<WriteFRcp, [SKLPort0], 5>; // Floating point reciprocal estimate.
-defm : SKLWriteResPair<WriteFRsqrt, [SKLPort0], 5>; // Floating point reciprocal square root estimate.
+defm : SKLWriteResPair<WriteFRcp, [SKLPort0], 4>; // Floating point reciprocal estimate.
+defm : SKLWriteResPair<WriteFRsqrt, [SKLPort0], 4>; // Floating point reciprocal square root estimate.
defm : SKLWriteResPair<WriteFMA, [SKLPort01], 4>; // Fused Multiply Add.
defm : SKLWriteResPair<WriteFSign, [SKLPort0], 1>; // Floating point fabs/fchs.
defm : SKLWriteResPair<WriteFLogic, [SKLPort015], 1, [1], 1, 6>; // Floating point and/or/xor logicals.
@@ -972,11 +972,7 @@ def: InstRW<[SKLWriteResGroup47], (instr
"MMX_PMULUDQirr",
"MUL_FPrST0",
"MUL_FST0r",
- "MUL_FrST0",
- "(V?)RCPPS(Y?)r",
- "(V?)RCPSSr",
- "(V?)RSQRTPS(Y?)r",
- "(V?)RSQRTSSr")>;
+ "MUL_FrST0")>;
def SKLWriteResGroup48 : SchedWriteRes<[SKLPort01]> {
let Latency = 4;
Modified: llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td?rev=330510&r1=330509&r2=330510&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td Sat Apr 21 08:16:59 2018
@@ -157,8 +157,8 @@ defm : SKXWriteResPair<WriteFCom, [SKX
defm : SKXWriteResPair<WriteFMul, [SKXPort0], 5>; // Floating point multiplication.
defm : SKXWriteResPair<WriteFDiv, [SKXPort0], 12>; // 10-14 cycles. // Floating point division.
defm : SKXWriteResPair<WriteFSqrt, [SKXPort0], 15>; // Floating point square root.
-defm : SKXWriteResPair<WriteFRcp, [SKXPort0], 5>; // Floating point reciprocal estimate.
-defm : SKXWriteResPair<WriteFRsqrt, [SKXPort0], 5>; // Floating point reciprocal square root estimate.
+defm : SKXWriteResPair<WriteFRcp, [SKXPort0], 4>; // Floating point reciprocal estimate.
+defm : SKXWriteResPair<WriteFRsqrt, [SKXPort0], 4>; // Floating point reciprocal square root estimate.
defm : SKXWriteResPair<WriteFMA, [SKXPort015], 4>; // Fused Multiply Add.
defm : SKXWriteResPair<WriteFSign, [SKXPort0], 1>; // Floating point fabs/fchs.
defm : SKXWriteResPair<WriteFLogic, [SKXPort015], 1, [1], 1, 6>; // Floating point and/or/xor logicals.
@@ -1898,29 +1898,7 @@ def: InstRW<[SKXWriteResGroup49], (instr
"MMX_PMULUDQirr",
"MUL_FPrST0",
"MUL_FST0r",
- "MUL_FrST0",
- "RCPPSr",
- "RCPSSr",
- "RSQRTPSr",
- "RSQRTSSr",
- "VRCP14PDZ128r",
- "VRCP14PDZ256r",
- "VRCP14PSZ128r",
- "VRCP14PSZ256r",
- "VRCP14SDrr",
- "VRCP14SSrr",
- "VRCPPSYr",
- "VRCPPSr",
- "VRCPSSr",
- "VRSQRT14PDZ128r",
- "VRSQRT14PDZ256r",
- "VRSQRT14PSZ128r",
- "VRSQRT14PSZ256r",
- "VRSQRT14SDrr",
- "VRSQRT14SSrr",
- "VRSQRTPSYr",
- "VRSQRTPSr",
- "VRSQRTSSr")>;
+ "MUL_FrST0")>;
def SKXWriteResGroup50 : SchedWriteRes<[SKXPort015]> {
let Latency = 4;
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