[PATCH] D45651: [X86] Add DAG combine to turn (trunc (srl (mul ext, ext), 16) into PMULHW/PMULHUW.

[Sanjay Patel via Phabricator via llvm-commits]

spatel added inline comments.


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Comment at: lib/Target/X86/X86ISelLowering.cpp:35997-35998
 
+// Try to form a MULHU or MULHS node by looking for
+// (trunc (srl (mul ext, ext), 16))
+static SDValue combinePMULH(SDValue Src, EVT VT, const SDLoc &DL,
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A top-level 'TODO' comment copying the reasoning for this being x86-specific would be good...in case someone fixes the common DAG problems and puts this in DAGCombiner, we'll know this can go.


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Comment at: lib/Target/X86/X86ISelLowering.cpp:36001
+                            SelectionDAG &DAG, const X86Subtarget &Subtarget) {
+  // First insruction should be a right shift of a multiply.
+  if (Src.getOpcode() != ISD::SRL ||
----------------
typo - 'instruction'


Repository:
  rL LLVM

https://reviews.llvm.org/D45651