[llvm] r330501 - [X86] Strip unnecessary x87 instruction instrw overrides from scheduler models.
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Sat Apr 21 04:25:02 PDT 2018
Author: rksimon
Date: Sat Apr 21 04:25:02 2018
New Revision: 330501
URL: http://llvm.org/viewvc/llvm-project?rev=330501&view=rev
Log:
[X86] Strip unnecessary x87 instruction instrw overrides from scheduler models.
Modified:
llvm/trunk/lib/Target/X86/X86SchedBroadwell.td
llvm/trunk/lib/Target/X86/X86SchedHaswell.td
llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td
Modified: llvm/trunk/lib/Target/X86/X86SchedBroadwell.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedBroadwell.td?rev=330501&r1=330500&r2=330501&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedBroadwell.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedBroadwell.td Sat Apr 21 04:25:02 2018
@@ -765,20 +765,11 @@ def BWWriteResGroup27 : SchedWriteRes<[B
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[BWWriteResGroup27], (instregex "ADD_FPrST0",
- "ADD_FST0r",
- "ADD_FrST0",
- "MMX_CVTPI2PSirr",
+def: InstRW<[BWWriteResGroup27], (instregex "MMX_CVTPI2PSirr",
"PDEP(32|64)rr",
"PEXT(32|64)rr",
"SHLD(16|32|64)rri8",
"SHRD(16|32|64)rri8",
- "SUBR_FPrST0",
- "SUBR_FST0r",
- "SUBR_FrST0",
- "SUB_FPrST0",
- "SUB_FST0r",
- "SUB_FrST0",
"(V?)CVTDQ2PS(Y?)rr",
"(V?)CVTPS2DQ(Y?)rr",
"(V?)CVTTPS2DQ(Y?)rr")>;
@@ -1028,9 +1019,6 @@ def: InstRW<[BWWriteResGroup47], (instre
"MMX_PMULHWirr",
"MMX_PMULLWirr",
"MMX_PMULUDQirr",
- "MUL_FPrST0",
- "MUL_FST0r",
- "MUL_FrST0",
"(V?)PCMPGTQ(Y?)rr",
"(V?)PHMINPOSUWrr",
"(V?)PMADDUBSW(Y?)rr",
Modified: llvm/trunk/lib/Target/X86/X86SchedHaswell.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedHaswell.td?rev=330501&r1=330500&r2=330501&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedHaswell.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedHaswell.td Sat Apr 21 04:25:02 2018
@@ -1643,20 +1643,11 @@ def HWWriteResGroup50 : SchedWriteRes<[H
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[HWWriteResGroup50], (instregex "ADD_FPrST0",
- "ADD_FST0r",
- "ADD_FrST0",
- "MMX_CVTPI2PSirr",
+def: InstRW<[HWWriteResGroup50], (instregex "MMX_CVTPI2PSirr",
"PDEP(32|64)rr",
"PEXT(32|64)rr",
"SHLD(16|32|64)rri8",
"SHRD(16|32|64)rri8",
- "SUBR_FPrST0",
- "SUBR_FST0r",
- "SUBR_FrST0",
- "SUB_FPrST0",
- "SUB_FST0r",
- "SUB_FrST0",
"(V?)ADDPD(Y?)rr",
"(V?)ADDPS(Y?)rr",
"(V?)ADDSDrr",
@@ -2189,9 +2180,6 @@ def: InstRW<[HWWriteResGroup89], (instre
"MMX_PMULHWirr",
"MMX_PMULLWirr",
"MMX_PMULUDQirr",
- "MUL_FPrST0",
- "MUL_FST0r",
- "MUL_FrST0",
"(V?)PCMPGTQ(Y?)rr",
"(V?)PHMINPOSUWrr",
"(V?)PMADDUBSW(Y?)rr",
Modified: llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td?rev=330501&r1=330500&r2=330501&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td Sat Apr 21 04:25:02 2018
@@ -587,17 +587,8 @@ def SBWriteResGroup21 : SchedWriteRes<[S
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[SBWriteResGroup21], (instregex "ADD_FPrST0",
- "ADD_FST0r",
- "ADD_FrST0",
- "MMX_CVTPI2PSirr",
+def: InstRW<[SBWriteResGroup21], (instregex "MMX_CVTPI2PSirr",
"PUSHFS64",
- "SUBR_FPrST0",
- "SUBR_FST0r",
- "SUBR_FrST0",
- "SUB_FPrST0",
- "SUB_FST0r",
- "SUB_FrST0",
"(V?)CVTDQ2PS(Y?)rr",
"(V?)CVTPS2DQ(Y?)rr",
"(V?)CVTTPS2DQ(Y?)rr")>;
@@ -761,10 +752,7 @@ def SBWriteResGroup30 : SchedWriteRes<[S
let NumMicroOps = 1;
let ResourceCycles = [1];
}
-def: InstRW<[SBWriteResGroup30], (instregex "MUL_FPrST0",
- "MUL_FST0r",
- "MUL_FrST0",
- "(V?)PCMPGTQrr")>;
+def: InstRW<[SBWriteResGroup30], (instregex "(V?)PCMPGTQrr")>;
def SBWriteResGroup31 : SchedWriteRes<[SBPort23]> {
let Latency = 5;
@@ -1807,18 +1795,6 @@ def SBWriteResGroup126 : SchedWriteRes<[
def: InstRW<[SBWriteResGroup126], (instregex "(V?)DIVPDrr",
"(V?)DIVSDrr")>;
-def SBWriteResGroup127 : SchedWriteRes<[SBPort0]> {
- let Latency = 24;
- let NumMicroOps = 1;
- let ResourceCycles = [1];
-}
-def: InstRW<[SBWriteResGroup127], (instregex "DIVR_FPrST0",
- "DIVR_FST0r",
- "DIVR_FrST0",
- "DIV_FPrST0",
- "DIV_FST0r",
- "DIV_FrST0")>;
-
def SBWriteResGroup128 : SchedWriteRes<[SBPort0,SBPort23,SBFPDivider]> {
let Latency = 28;
let NumMicroOps = 2;
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