[llvm] r330415 - [NFC][InstCombine] Regenerate two tests that are affected by folding masked merge
Roman Lebedev via llvm-commits
llvm-commits at lists.llvm.org
Fri Apr 20 03:49:19 PDT 2018
Author: lebedevri
Date: Fri Apr 20 03:49:19 2018
New Revision: 330415
URL: http://llvm.org/viewvc/llvm-project?rev=330415&view=rev
Log:
[NFC][InstCombine] Regenerate two tests that are affected by folding masked merge
Modified:
llvm/trunk/test/Transforms/InstCombine/or.ll
llvm/trunk/test/Transforms/InstCombine/vec_sext.ll
Modified: llvm/trunk/test/Transforms/InstCombine/or.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/or.ll?rev=330415&r1=330414&r2=330415&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/or.ll (original)
+++ llvm/trunk/test/Transforms/InstCombine/or.ll Fri Apr 20 03:49:19 2018
@@ -6,7 +6,7 @@ target datalayout = "e-p:32:32:32-i1:8:8
define i32 @test12(i32 %A) {
; Should be eliminated
; CHECK-LABEL: @test12(
-; CHECK-NEXT: [[C:%.*]] = and i32 %A, 8
+; CHECK-NEXT: [[C:%.*]] = and i32 [[A:%.*]], 8
; CHECK-NEXT: ret i32 [[C]]
;
%B = or i32 %A, 4
@@ -26,7 +26,7 @@ define i32 @test13(i32 %A) {
define i1 @test14(i32 %A, i32 %B) {
; CHECK-LABEL: @test14(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i32 %A, %B
+; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i32 [[A:%.*]], [[B:%.*]]
; CHECK-NEXT: ret i1 [[TMP1]]
;
%C1 = icmp ult i32 %A, %B
@@ -38,7 +38,7 @@ define i1 @test14(i32 %A, i32 %B) {
define i1 @test15(i32 %A, i32 %B) {
; CHECK-LABEL: @test15(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ule i32 %A, %B
+; CHECK-NEXT: [[TMP1:%.*]] = icmp ule i32 [[A:%.*]], [[B:%.*]]
; CHECK-NEXT: ret i1 [[TMP1]]
;
%C1 = icmp ult i32 %A, %B
@@ -50,7 +50,7 @@ define i1 @test15(i32 %A, i32 %B) {
define i32 @test16(i32 %A) {
; CHECK-LABEL: @test16(
-; CHECK-NEXT: ret i32 %A
+; CHECK-NEXT: ret i32 [[A:%.*]]
;
%B = and i32 %A, 1
; -2 = ~1
@@ -62,7 +62,7 @@ define i32 @test16(i32 %A) {
define i32 @test17(i32 %A) {
; CHECK-LABEL: @test17(
-; CHECK-NEXT: [[D:%.*]] = and i32 %A, 5
+; CHECK-NEXT: [[D:%.*]] = and i32 [[A:%.*]], 5
; CHECK-NEXT: ret i32 [[D]]
;
%B = and i32 %A, 1
@@ -74,7 +74,7 @@ define i32 @test17(i32 %A) {
define i1 @test18(i32 %A) {
; CHECK-LABEL: @test18(
-; CHECK-NEXT: [[A_OFF:%.*]] = add i32 %A, -50
+; CHECK-NEXT: [[A_OFF:%.*]] = add i32 [[A:%.*]], -50
; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i32 [[A_OFF]], 49
; CHECK-NEXT: ret i1 [[TMP1]]
;
@@ -87,8 +87,8 @@ define i1 @test18(i32 %A) {
; FIXME: Vectors should fold too.
define <2 x i1> @test18vec(<2 x i32> %A) {
; CHECK-LABEL: @test18vec(
-; CHECK-NEXT: [[B:%.*]] = icmp sgt <2 x i32> %A, <i32 99, i32 99>
-; CHECK-NEXT: [[C:%.*]] = icmp slt <2 x i32> %A, <i32 50, i32 50>
+; CHECK-NEXT: [[B:%.*]] = icmp sgt <2 x i32> [[A:%.*]], <i32 99, i32 99>
+; CHECK-NEXT: [[C:%.*]] = icmp slt <2 x i32> [[A]], <i32 50, i32 50>
; CHECK-NEXT: [[D:%.*]] = or <2 x i1> [[B]], [[C]]
; CHECK-NEXT: ret <2 x i1> [[D]]
;
@@ -100,7 +100,7 @@ define <2 x i1> @test18vec(<2 x i32> %A)
define i32 @test20(i32 %x) {
; CHECK-LABEL: @test20(
-; CHECK-NEXT: ret i32 %x
+; CHECK-NEXT: ret i32 [[X:%.*]]
;
%y = and i32 %x, 123
%z = or i32 %y, %x
@@ -109,7 +109,7 @@ define i32 @test20(i32 %x) {
define i32 @test21(i32 %tmp.1) {
; CHECK-LABEL: @test21(
-; CHECK-NEXT: [[TMP_1_MASK1:%.*]] = add i32 %tmp.1, 2
+; CHECK-NEXT: [[TMP_1_MASK1:%.*]] = add i32 [[TMP_1:%.*]], 2
; CHECK-NEXT: ret i32 [[TMP_1_MASK1]]
;
%tmp.1.mask1 = add i32 %tmp.1, 2
@@ -122,7 +122,7 @@ define i32 @test21(i32 %tmp.1) {
define i32 @test22(i32 %B) {
; CHECK-LABEL: @test22(
-; CHECK-NEXT: ret i32 %B
+; CHECK-NEXT: ret i32 [[B:%.*]]
;
%ELIM41 = and i32 %B, 1
%ELIM7 = and i32 %B, -2
@@ -132,7 +132,7 @@ define i32 @test22(i32 %B) {
define i16 @test23(i16 %A) {
; CHECK-LABEL: @test23(
-; CHECK-NEXT: [[B:%.*]] = lshr i16 %A, 1
+; CHECK-NEXT: [[B:%.*]] = lshr i16 [[A:%.*]], 1
; CHECK-NEXT: [[D:%.*]] = xor i16 [[B]], -24575
; CHECK-NEXT: ret i16 [[D]]
;
@@ -159,9 +159,9 @@ define <2 x i16> @test23vec(<2 x i16> %A
; PR3266 & PR5276
define i1 @test25(i32 %A, i32 %B) {
; CHECK-LABEL: @test25(
-; CHECK-NEXT: [[NOTLHS:%.*]] = icmp ne i32 %A, 0
-; CHECK-NEXT: [[NOTRHS:%.*]] = icmp ne i32 %B, 57
-; CHECK-NEXT: [[F:%.*]] = and i1 [[NOTRHS]], [[NOTLHS]]
+; CHECK-NEXT: [[C:%.*]] = icmp ne i32 [[A:%.*]], 0
+; CHECK-NEXT: [[D:%.*]] = icmp ne i32 [[B:%.*]], 57
+; CHECK-NEXT: [[F:%.*]] = and i1 [[D]], [[C]]
; CHECK-NEXT: ret i1 [[F]]
;
%C = icmp eq i32 %A, 0
@@ -174,7 +174,7 @@ define i1 @test25(i32 %A, i32 %B) {
; PR5634
define i1 @test26(i32 %A, i32 %B) {
; CHECK-LABEL: @test26(
-; CHECK-NEXT: [[TMP1:%.*]] = or i32 %A, %B
+; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[A:%.*]], [[B:%.*]]
; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 0
; CHECK-NEXT: ret i1 [[TMP2]]
;
@@ -187,8 +187,8 @@ define i1 @test26(i32 %A, i32 %B) {
define i1 @test27(i32* %A, i32* %B) {
; CHECK-LABEL: @test27(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i32* %A, null
-; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i32* %B, null
+; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i32* [[A:%.*]], null
+; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i32* [[B:%.*]], null
; CHECK-NEXT: [[E:%.*]] = and i1 [[TMP1]], [[TMP2]]
; CHECK-NEXT: ret i1 [[E]]
;
@@ -201,8 +201,8 @@ define i1 @test27(i32* %A, i32* %B) {
define <2 x i1> @test27vec(<2 x i32*> %A, <2 x i32*> %B) {
; CHECK-LABEL: @test27vec(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <2 x i32*> %A, zeroinitializer
-; CHECK-NEXT: [[TMP2:%.*]] = icmp eq <2 x i32*> %B, zeroinitializer
+; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <2 x i32*> [[A:%.*]], zeroinitializer
+; CHECK-NEXT: [[TMP2:%.*]] = icmp eq <2 x i32*> [[B:%.*]], zeroinitializer
; CHECK-NEXT: [[E:%.*]] = and <2 x i1> [[TMP1]], [[TMP2]]
; CHECK-NEXT: ret <2 x i1> [[E]]
;
@@ -216,7 +216,7 @@ define <2 x i1> @test27vec(<2 x i32*> %A
; PR5634
define i1 @test28(i32 %A, i32 %B) {
; CHECK-LABEL: @test28(
-; CHECK-NEXT: [[TMP1:%.*]] = or i32 %A, %B
+; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[A:%.*]], [[B:%.*]]
; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0
; CHECK-NEXT: ret i1 [[TMP2]]
;
@@ -229,8 +229,8 @@ define i1 @test28(i32 %A, i32 %B) {
define i1 @test29(i32* %A, i32* %B) {
; CHECK-LABEL: @test29(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i32* %A, null
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i32* %B, null
+; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i32* [[A:%.*]], null
+; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i32* [[B:%.*]], null
; CHECK-NEXT: [[E:%.*]] = or i1 [[TMP1]], [[TMP2]]
; CHECK-NEXT: ret i1 [[E]]
;
@@ -243,8 +243,8 @@ define i1 @test29(i32* %A, i32* %B) {
define <2 x i1> @test29vec(<2 x i32*> %A, <2 x i32*> %B) {
; CHECK-LABEL: @test29vec(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ne <2 x i32*> %A, zeroinitializer
-; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <2 x i32*> %B, zeroinitializer
+; CHECK-NEXT: [[TMP1:%.*]] = icmp ne <2 x i32*> [[A:%.*]], zeroinitializer
+; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <2 x i32*> [[B:%.*]], zeroinitializer
; CHECK-NEXT: [[E:%.*]] = or <2 x i1> [[TMP1]], [[TMP2]]
; CHECK-NEXT: ret <2 x i1> [[E]]
;
@@ -258,7 +258,7 @@ define <2 x i1> @test29vec(<2 x i32*> %A
; PR4216
define i32 @test30(i32 %A) {
; CHECK-LABEL: @test30(
-; CHECK-NEXT: [[D:%.*]] = and i32 %A, -58312
+; CHECK-NEXT: [[D:%.*]] = and i32 [[A:%.*]], -58312
; CHECK-NEXT: [[E:%.*]] = or i32 [[D]], 32962
; CHECK-NEXT: ret i32 [[E]]
;
@@ -287,7 +287,7 @@ define <2 x i32> @test30vec(<2 x i32> %A
; PR4216
define i64 @test31(i64 %A) {
; CHECK-LABEL: @test31(
-; CHECK-NEXT: [[E:%.*]] = and i64 %A, 4294908984
+; CHECK-NEXT: [[E:%.*]] = and i64 [[A:%.*]], 4294908984
; CHECK-NEXT: [[F:%.*]] = or i64 [[E]], 32962
; CHECK-NEXT: ret i64 [[F]]
;
@@ -320,8 +320,8 @@ define <2 x i64> @test31vec(<2 x i64> %A
; codegen is mature enough to handle vector selects.
define <4 x i32> @test32(<4 x i1> %and.i1352, <4 x i32> %vecinit6.i176, <4 x i32> %vecinit6.i191) {
; CHECK-LABEL: @test32(
-; CHECK-NEXT: [[OR_I:%.*]] = select <4 x i1> %and.i1352, <4 x i32> %vecinit6.i176, <4 x i32> %vecinit6.i191
-; CHECK-NEXT: ret <4 x i32> [[OR_I]]
+; CHECK-NEXT: [[TMP1:%.*]] = select <4 x i1> [[AND_I1352:%.*]], <4 x i32> [[VECINIT6_I176:%.*]], <4 x i32> [[VECINIT6_I191:%.*]]
+; CHECK-NEXT: ret <4 x i32> [[TMP1]]
;
%and.i135 = sext <4 x i1> %and.i1352 to <4 x i32>
%and.i129 = and <4 x i32> %vecinit6.i176, %and.i135
@@ -333,7 +333,7 @@ define <4 x i32> @test32(<4 x i1> %and.i
define i1 @test33(i1 %X, i1 %Y) {
; CHECK-LABEL: @test33(
-; CHECK-NEXT: [[B:%.*]] = or i1 %X, %Y
+; CHECK-NEXT: [[B:%.*]] = or i1 [[X:%.*]], [[Y:%.*]]
; CHECK-NEXT: ret i1 [[B]]
;
%a = or i1 %X, %Y
@@ -343,7 +343,7 @@ define i1 @test33(i1 %X, i1 %Y) {
define i32 @test34(i32 %X, i32 %Y) {
; CHECK-LABEL: @test34(
-; CHECK-NEXT: [[B:%.*]] = or i32 %X, %Y
+; CHECK-NEXT: [[B:%.*]] = or i32 [[X:%.*]], [[Y:%.*]]
; CHECK-NEXT: ret i32 [[B]]
;
%a = or i32 %X, %Y
@@ -353,7 +353,7 @@ define i32 @test34(i32 %X, i32 %Y) {
define i32 @test35(i32 %a, i32 %b) {
; CHECK-LABEL: @test35(
-; CHECK-NEXT: [[TMP1:%.*]] = or i32 %a, %b
+; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[A:%.*]], [[B:%.*]]
; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[TMP1]], 1135
; CHECK-NEXT: ret i32 [[TMP2]]
;
@@ -364,9 +364,9 @@ define i32 @test35(i32 %a, i32 %b) {
define i1 @test36(i32 %x) {
; CHECK-LABEL: @test36(
-; CHECK-NEXT: [[X_OFF:%.*]] = add i32 %x, -23
-; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i32 [[X_OFF]], 3
-; CHECK-NEXT: ret i1 [[TMP1]]
+; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[X:%.*]], -23
+; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i32 [[TMP1]], 3
+; CHECK-NEXT: ret i1 [[TMP2]]
;
%cmp1 = icmp eq i32 %x, 23
%cmp2 = icmp eq i32 %x, 24
@@ -378,7 +378,7 @@ define i1 @test36(i32 %x) {
define i32 @orsext_to_sel(i32 %x, i1 %y) {
; CHECK-LABEL: @orsext_to_sel(
-; CHECK-NEXT: [[OR:%.*]] = select i1 %y, i32 -1, i32 %x
+; CHECK-NEXT: [[OR:%.*]] = select i1 [[Y:%.*]], i32 -1, i32 [[X:%.*]]
; CHECK-NEXT: ret i32 [[OR]]
;
%sext = sext i1 %y to i32
@@ -388,7 +388,7 @@ define i32 @orsext_to_sel(i32 %x, i1 %y)
define i32 @orsext_to_sel_swap(i32 %x, i1 %y) {
; CHECK-LABEL: @orsext_to_sel_swap(
-; CHECK-NEXT: [[OR:%.*]] = select i1 %y, i32 -1, i32 %x
+; CHECK-NEXT: [[OR:%.*]] = select i1 [[Y:%.*]], i32 -1, i32 [[X:%.*]]
; CHECK-NEXT: ret i32 [[OR]]
;
%sext = sext i1 %y to i32
@@ -398,8 +398,8 @@ define i32 @orsext_to_sel_swap(i32 %x, i
define i32 @orsext_to_sel_multi_use(i32 %x, i1 %y) {
; CHECK-LABEL: @orsext_to_sel_multi_use(
-; CHECK-NEXT: [[SEXT:%.*]] = sext i1 %y to i32
-; CHECK-NEXT: [[OR:%.*]] = or i32 [[SEXT]], %x
+; CHECK-NEXT: [[SEXT:%.*]] = sext i1 [[Y:%.*]] to i32
+; CHECK-NEXT: [[OR:%.*]] = or i32 [[SEXT]], [[X:%.*]]
; CHECK-NEXT: [[ADD:%.*]] = add i32 [[OR]], [[SEXT]]
; CHECK-NEXT: ret i32 [[ADD]]
;
@@ -411,7 +411,7 @@ define i32 @orsext_to_sel_multi_use(i32
define <2 x i32> @orsext_to_sel_vec(<2 x i32> %x, <2 x i1> %y) {
; CHECK-LABEL: @orsext_to_sel_vec(
-; CHECK-NEXT: [[OR:%.*]] = select <2 x i1> %y, <2 x i32> <i32 -1, i32 -1>, <2 x i32> %x
+; CHECK-NEXT: [[OR:%.*]] = select <2 x i1> [[Y:%.*]], <2 x i32> <i32 -1, i32 -1>, <2 x i32> [[X:%.*]]
; CHECK-NEXT: ret <2 x i32> [[OR]]
;
%sext = sext <2 x i1> %y to <2 x i32>
@@ -421,7 +421,7 @@ define <2 x i32> @orsext_to_sel_vec(<2 x
define <2 x i132> @orsext_to_sel_vec_swap(<2 x i132> %x, <2 x i1> %y) {
; CHECK-LABEL: @orsext_to_sel_vec_swap(
-; CHECK-NEXT: [[OR:%.*]] = select <2 x i1> %y, <2 x i132> <i132 -1, i132 -1>, <2 x i132> %x
+; CHECK-NEXT: [[OR:%.*]] = select <2 x i1> [[Y:%.*]], <2 x i132> <i132 -1, i132 -1>, <2 x i132> [[X:%.*]]
; CHECK-NEXT: ret <2 x i132> [[OR]]
;
%sext = sext <2 x i1> %y to <2 x i132>
@@ -433,8 +433,8 @@ define <2 x i132> @orsext_to_sel_vec_swa
define i32 @test39a(i32 %a, float %b) {
; CHECK-LABEL: @test39a(
-; CHECK-NEXT: [[A1:%.*]] = mul i32 %a, 42
-; CHECK-NEXT: [[B1:%.*]] = bitcast float %b to i32
+; CHECK-NEXT: [[A1:%.*]] = mul i32 [[A:%.*]], 42
+; CHECK-NEXT: [[B1:%.*]] = bitcast float [[B:%.*]] to i32
; CHECK-NEXT: [[OR:%.*]] = or i32 [[A1]], [[B1]]
; CHECK-NEXT: ret i32 [[OR]]
;
@@ -451,8 +451,8 @@ define i32 @test39a(i32 %a, float %b) {
define i32 @test39b(i32 %a, float %b) {
; CHECK-LABEL: @test39b(
-; CHECK-NEXT: [[A1:%.*]] = mul i32 %a, 42
-; CHECK-NEXT: [[B1:%.*]] = bitcast float %b to i32
+; CHECK-NEXT: [[A1:%.*]] = mul i32 [[A:%.*]], 42
+; CHECK-NEXT: [[B1:%.*]] = bitcast float [[B:%.*]] to i32
; CHECK-NEXT: [[OR:%.*]] = or i32 [[A1]], [[B1]]
; CHECK-NEXT: ret i32 [[OR]]
;
@@ -469,8 +469,8 @@ define i32 @test39b(i32 %a, float %b) {
define i32 @test39c(i32 %a, float %b) {
; CHECK-LABEL: @test39c(
-; CHECK-NEXT: [[A1:%.*]] = mul i32 %a, 42
-; CHECK-NEXT: [[B1:%.*]] = bitcast float %b to i32
+; CHECK-NEXT: [[A1:%.*]] = mul i32 [[A:%.*]], 42
+; CHECK-NEXT: [[B1:%.*]] = bitcast float [[B:%.*]] to i32
; CHECK-NEXT: [[OR:%.*]] = or i32 [[A1]], [[B1]]
; CHECK-NEXT: ret i32 [[OR]]
;
@@ -487,8 +487,8 @@ define i32 @test39c(i32 %a, float %b) {
define i32 @test39d(i32 %a, float %b) {
; CHECK-LABEL: @test39d(
-; CHECK-NEXT: [[A1:%.*]] = mul i32 %a, 42
-; CHECK-NEXT: [[B1:%.*]] = bitcast float %b to i32
+; CHECK-NEXT: [[A1:%.*]] = mul i32 [[A:%.*]], 42
+; CHECK-NEXT: [[B1:%.*]] = bitcast float [[B:%.*]] to i32
; CHECK-NEXT: [[OR:%.*]] = or i32 [[A1]], [[B1]]
; CHECK-NEXT: ret i32 [[OR]]
;
@@ -502,8 +502,8 @@ define i32 @test39d(i32 %a, float %b) {
define i32 @test40(i32 %a, i32 %b) {
; CHECK-LABEL: @test40(
-; CHECK-NEXT: [[TMP1:%.*]] = xor i32 %a, -1
-; CHECK-NEXT: [[OR:%.*]] = or i32 [[TMP1]], %b
+; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[A:%.*]], -1
+; CHECK-NEXT: [[OR:%.*]] = or i32 [[XOR]], [[B:%.*]]
; CHECK-NEXT: ret i32 [[OR]]
;
%and = and i32 %a, %b
@@ -514,8 +514,8 @@ define i32 @test40(i32 %a, i32 %b) {
define i32 @test40b(i32 %a, i32 %b) {
; CHECK-LABEL: @test40b(
-; CHECK-NEXT: [[XOR:%.*]] = xor i32 %a, -1
-; CHECK-NEXT: [[OR:%.*]] = or i32 [[XOR]], %b
+; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[A:%.*]], -1
+; CHECK-NEXT: [[OR:%.*]] = or i32 [[XOR]], [[B:%.*]]
; CHECK-NEXT: ret i32 [[OR]]
;
%and = and i32 %b, %a
@@ -526,8 +526,8 @@ define i32 @test40b(i32 %a, i32 %b) {
define i32 @test40c(i32 %a, i32 %b) {
; CHECK-LABEL: @test40c(
-; CHECK-NEXT: [[XOR:%.*]] = xor i32 %a, -1
-; CHECK-NEXT: [[OR:%.*]] = or i32 [[XOR]], %b
+; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[A:%.*]], -1
+; CHECK-NEXT: [[OR:%.*]] = or i32 [[XOR]], [[B:%.*]]
; CHECK-NEXT: ret i32 [[OR]]
;
%and = and i32 %b, %a
@@ -538,8 +538,8 @@ define i32 @test40c(i32 %a, i32 %b) {
define i32 @test40d(i32 %a, i32 %b) {
; CHECK-LABEL: @test40d(
-; CHECK-NEXT: [[XOR:%.*]] = xor i32 %a, -1
-; CHECK-NEXT: [[OR:%.*]] = or i32 [[XOR]], %b
+; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[A:%.*]], -1
+; CHECK-NEXT: [[OR:%.*]] = or i32 [[XOR]], [[B:%.*]]
; CHECK-NEXT: ret i32 [[OR]]
;
%and = and i32 %a, %b
@@ -550,8 +550,8 @@ define i32 @test40d(i32 %a, i32 %b) {
define i32 @test45(i32 %x, i32 %y, i32 %z) {
; CHECK-LABEL: @test45(
-; CHECK-NEXT: [[TMP1:%.*]] = and i32 %x, %z
-; CHECK-NEXT: [[OR1:%.*]] = or i32 [[TMP1]], %y
+; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], [[Z:%.*]]
+; CHECK-NEXT: [[OR1:%.*]] = or i32 [[TMP1]], [[Y:%.*]]
; CHECK-NEXT: ret i32 [[OR1]]
;
%or = or i32 %y, %z
@@ -562,7 +562,7 @@ define i32 @test45(i32 %x, i32 %y, i32 %
define i1 @test46(i8 signext %c) {
; CHECK-LABEL: @test46(
-; CHECK-NEXT: [[TMP1:%.*]] = and i8 %c, -33
+; CHECK-NEXT: [[TMP1:%.*]] = and i8 [[C:%.*]], -33
; CHECK-NEXT: [[TMP2:%.*]] = add i8 [[TMP1]], -65
; CHECK-NEXT: [[TMP3:%.*]] = icmp ult i8 [[TMP2]], 26
; CHECK-NEXT: ret i1 [[TMP3]]
@@ -577,7 +577,7 @@ define i1 @test46(i8 signext %c) {
define i1 @test47(i8 signext %c) {
; CHECK-LABEL: @test47(
-; CHECK-NEXT: [[TMP1:%.*]] = and i8 %c, -33
+; CHECK-NEXT: [[TMP1:%.*]] = and i8 [[C:%.*]], -33
; CHECK-NEXT: [[TMP2:%.*]] = add i8 [[TMP1]], -65
; CHECK-NEXT: [[TMP3:%.*]] = icmp ult i8 [[TMP2]], 27
; CHECK-NEXT: ret i1 [[TMP3]]
Modified: llvm/trunk/test/Transforms/InstCombine/vec_sext.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/vec_sext.ll?rev=330415&r1=330414&r2=330415&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/vec_sext.ll (original)
+++ llvm/trunk/test/Transforms/InstCombine/vec_sext.ll Fri Apr 20 03:49:19 2018
@@ -3,11 +3,11 @@
define <4 x i32> @psignd_3(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: @psignd_3(
-; CHECK-NEXT: [[SUB:%.*]] = sub nsw <4 x i32> zeroinitializer, %a
-; CHECK-NEXT: [[B_LOBIT:%.*]] = ashr <4 x i32> %b, <i32 31, i32 31, i32 31, i32 31>
-; CHECK-NEXT: [[T1:%.*]] = xor <4 x i32> [[B_LOBIT]], <i32 -1, i32 -1, i32 -1, i32 -1>
-; CHECK-NEXT: [[T2:%.*]] = and <4 x i32> [[T1]], %a
-; CHECK-NEXT: [[T3:%.*]] = and <4 x i32> [[B_LOBIT]], [[SUB]]
+; CHECK-NEXT: [[SUB:%.*]] = sub nsw <4 x i32> zeroinitializer, [[A:%.*]]
+; CHECK-NEXT: [[B_LOBIT1:%.*]] = ashr <4 x i32> [[B:%.*]], <i32 31, i32 31, i32 31, i32 31>
+; CHECK-NEXT: [[T1:%.*]] = xor <4 x i32> [[B_LOBIT1]], <i32 -1, i32 -1, i32 -1, i32 -1>
+; CHECK-NEXT: [[T2:%.*]] = and <4 x i32> [[T1]], [[A]]
+; CHECK-NEXT: [[T3:%.*]] = and <4 x i32> [[B_LOBIT1]], [[SUB]]
; CHECK-NEXT: [[COND:%.*]] = or <4 x i32> [[T2]], [[T3]]
; CHECK-NEXT: ret <4 x i32> [[COND]]
;
@@ -25,11 +25,11 @@ define <4 x i32> @psignd_3(<4 x i32> %a,
define <4 x i32> @test1(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: @test1(
-; CHECK-NEXT: [[SUB:%.*]] = sub nsw <4 x i32> zeroinitializer, %a
-; CHECK-NEXT: [[B_LOBIT:%.*]] = ashr <4 x i32> %b, <i32 31, i32 31, i32 31, i32 31>
-; CHECK-NEXT: [[B_LOBIT_NOT:%.*]] = xor <4 x i32> [[B_LOBIT]], <i32 -1, i32 -1, i32 -1, i32 -1>
-; CHECK-NEXT: [[T2:%.*]] = and <4 x i32> [[B_LOBIT]], %a
-; CHECK-NEXT: [[T3:%.*]] = and <4 x i32> [[B_LOBIT_NOT]], [[SUB]]
+; CHECK-NEXT: [[SUB:%.*]] = sub nsw <4 x i32> zeroinitializer, [[A:%.*]]
+; CHECK-NEXT: [[B_LOBIT1:%.*]] = ashr <4 x i32> [[B:%.*]], <i32 31, i32 31, i32 31, i32 31>
+; CHECK-NEXT: [[B_LOBIT1_NOT:%.*]] = xor <4 x i32> [[B_LOBIT1]], <i32 -1, i32 -1, i32 -1, i32 -1>
+; CHECK-NEXT: [[T2:%.*]] = and <4 x i32> [[B_LOBIT1]], [[A]]
+; CHECK-NEXT: [[T3:%.*]] = and <4 x i32> [[B_LOBIT1_NOT]], [[SUB]]
; CHECK-NEXT: [[COND:%.*]] = or <4 x i32> [[T2]], [[T3]]
; CHECK-NEXT: ret <4 x i32> [[COND]]
;
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