[llvm] r330365 - [AMDGPU] Use packed literals with zero either lower or hi part
Stanislav Mekhanoshin via llvm-commits
llvm-commits at lists.llvm.org
Thu Apr 19 14:16:50 PDT 2018
Author: rampitec
Date: Thu Apr 19 14:16:50 2018
New Revision: 330365
URL: http://llvm.org/viewvc/llvm-project?rev=330365&view=rev
Log:
[AMDGPU] Use packed literals with zero either lower or hi part
Differential Revision: https://reviews.llvm.org/D45790
Added:
llvm/trunk/test/CodeGen/AMDGPU/pk_max_f16_literal.ll
Modified:
llvm/trunk/lib/Target/AMDGPU/SIFoldOperands.cpp
llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp
llvm/trunk/test/CodeGen/AMDGPU/add.v2i16.ll
llvm/trunk/test/CodeGen/AMDGPU/immv216.ll
llvm/trunk/test/CodeGen/AMDGPU/sub.v2i16.ll
Modified: llvm/trunk/lib/Target/AMDGPU/SIFoldOperands.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIFoldOperands.cpp?rev=330365&r1=330364&r2=330365&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIFoldOperands.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIFoldOperands.cpp Thu Apr 19 14:16:50 2018
@@ -156,7 +156,8 @@ static bool updateOperand(FoldCandidate
if (Fold.isImm()) {
if (MI->getDesc().TSFlags & SIInstrFlags::IsPacked) {
- // Set op_sel_hi on this operand or bail out if op_sel is already set.
+ // Set op_sel/op_sel_hi on this operand or bail out if op_sel is
+ // already set.
unsigned Opcode = MI->getOpcode();
int OpNo = MI->getOperandNo(&Old);
int ModIdx = -1;
@@ -172,7 +173,16 @@ static bool updateOperand(FoldCandidate
unsigned Val = Mod.getImm();
if ((Val & SISrcMods::OP_SEL_0) || !(Val & SISrcMods::OP_SEL_1))
return false;
- Mod.setImm(Mod.getImm() & ~SISrcMods::OP_SEL_1);
+ // If upper part is all zero we do not need op_sel_hi.
+ if (!isUInt<16>(Fold.ImmToFold)) {
+ if (!(Fold.ImmToFold & 0xffff)) {
+ Mod.setImm(Mod.getImm() | SISrcMods::OP_SEL_0);
+ Mod.setImm(Mod.getImm() & ~SISrcMods::OP_SEL_1);
+ Old.ChangeToImmediate(Fold.ImmToFold >> 16);
+ return true;
+ }
+ Mod.setImm(Mod.getImm() & ~SISrcMods::OP_SEL_1);
+ }
}
Old.ChangeToImmediate(Fold.ImmToFold);
return true;
Modified: llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp?rev=330365&r1=330364&r2=330365&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp Thu Apr 19 14:16:50 2018
@@ -2339,6 +2339,15 @@ bool SIInstrInfo::isInlineConstant(const
}
case AMDGPU::OPERAND_REG_INLINE_C_V2INT16:
case AMDGPU::OPERAND_REG_INLINE_C_V2FP16: {
+ if (isUInt<16>(Imm)) {
+ int16_t Trunc = static_cast<int16_t>(Imm);
+ return ST.has16BitInsts() &&
+ AMDGPU::isInlinableLiteral16(Trunc, ST.hasInv2PiInlineImm());
+ }
+ if (!(Imm & 0xffff)) {
+ return ST.has16BitInsts() &&
+ AMDGPU::isInlinableLiteral16(Imm >> 16, ST.hasInv2PiInlineImm());
+ }
uint32_t Trunc = static_cast<uint32_t>(Imm);
return AMDGPU::isInlinableLiteralV216(Trunc, ST.hasInv2PiInlineImm());
}
Modified: llvm/trunk/test/CodeGen/AMDGPU/add.v2i16.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/add.v2i16.ll?rev=330365&r1=330364&r2=330365&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/add.v2i16.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/add.v2i16.ll Thu Apr 19 14:16:50 2018
@@ -115,8 +115,7 @@ define amdgpu_kernel void @v_test_add_v2
}
; GCN-LABEL: {{^}}v_test_add_v2i16_inline_lo_zero_hi:
-; GFX9: s_mov_b32 [[K:s[0-9]+]], 32{{$}}
-; GFX9: v_pk_add_u16 v{{[0-9]+}}, v{{[0-9]+}}, [[K]]{{$}}
+; GFX9: v_pk_add_u16 v{{[0-9]+}}, v{{[0-9]+}}, 32{{$}}
; VI-NOT: v_add_u16
; VI: v_add_u16_e32 v{{[0-9]+}}, 32, v{{[0-9]+}}
Modified: llvm/trunk/test/CodeGen/AMDGPU/immv216.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/immv216.ll?rev=330365&r1=330364&r2=330365&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/immv216.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/immv216.ll Thu Apr 19 14:16:50 2018
@@ -117,7 +117,7 @@ define amdgpu_kernel void @store_literal
; GCN-LABEL: {{^}}add_inline_imm_0.0_v2f16:
; GFX9: s_load_dword [[VAL:s[0-9]+]]
-; GFX9: v_pk_add_f16 [[REG:v[0-9]+]], [[VAL]], 0 op_sel_hi:[1,0]{{$}}
+; GFX9: v_pk_add_f16 [[REG:v[0-9]+]], [[VAL]], 0{{$}}
; GFX9: buffer_store_dword [[REG]]
; VI: buffer_load_ushort [[VAL0:v[0-9]+]]
Added: llvm/trunk/test/CodeGen/AMDGPU/pk_max_f16_literal.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/pk_max_f16_literal.ll?rev=330365&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/pk_max_f16_literal.ll (added)
+++ llvm/trunk/test/CodeGen/AMDGPU/pk_max_f16_literal.ll Thu Apr 19 14:16:50 2018
@@ -0,0 +1,95 @@
+; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9 %s
+
+; GCN-LABEL: {{^}}test_pk_max_f16_literal_0_1:
+; GFX9: v_pk_max_f16 v{{[0-9]+}}, v{{[0-9]+}}, 1.0 op_sel:[0,1] op_sel_hi:[1,0]{{$}}
+define amdgpu_kernel void @test_pk_max_f16_literal_0_1(<2 x half> addrspace(1)* nocapture %arg) {
+bb:
+ %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
+ %tmp1 = zext i32 %tmp to i64
+ %tmp2 = getelementptr inbounds <2 x half>, <2 x half> addrspace(1)* %arg, i64 %tmp1
+ %tmp3 = load <2 x half>, <2 x half> addrspace(1)* %tmp2, align 4
+ %tmp4 = tail call <2 x half> @llvm.maxnum.v2f16(<2 x half> %tmp3, <2 x half> <half 0xH0000, half 0xH3C00>)
+ store <2 x half> %tmp4, <2 x half> addrspace(1)* %tmp2, align 4
+ ret void
+}
+
+; GCN-LABEL: {{^}}test_pk_max_f16_literal_1_0:
+; GFX9: v_pk_max_f16 v{{[0-9]+}}, v{{[0-9]+}}, 1.0{{$}}
+define amdgpu_kernel void @test_pk_max_f16_literal_1_0(<2 x half> addrspace(1)* nocapture %arg) {
+bb:
+ %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
+ %tmp1 = zext i32 %tmp to i64
+ %tmp2 = getelementptr inbounds <2 x half>, <2 x half> addrspace(1)* %arg, i64 %tmp1
+ %tmp3 = load <2 x half>, <2 x half> addrspace(1)* %tmp2, align 4
+ %tmp4 = tail call <2 x half> @llvm.maxnum.v2f16(<2 x half> %tmp3, <2 x half> <half 0xH3C00, half 0xH0000>)
+ store <2 x half> %tmp4, <2 x half> addrspace(1)* %tmp2, align 4
+ ret void
+}
+
+; GCN-LABEL: {{^}}test_pk_max_f16_literal_1_1:
+; GFX9: v_pk_max_f16 v{{[0-9]+}}, v{{[0-9]+}}, 1.0 op_sel_hi:[1,0]{{$}}
+define amdgpu_kernel void @test_pk_max_f16_literal_1_1(<2 x half> addrspace(1)* nocapture %arg) {
+bb:
+ %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
+ %tmp1 = zext i32 %tmp to i64
+ %tmp2 = getelementptr inbounds <2 x half>, <2 x half> addrspace(1)* %arg, i64 %tmp1
+ %tmp3 = load <2 x half>, <2 x half> addrspace(1)* %tmp2, align 4
+ %tmp4 = tail call <2 x half> @llvm.maxnum.v2f16(<2 x half> %tmp3, <2 x half> <half 0xH3C00, half 0xH3C00>)
+ store <2 x half> %tmp4, <2 x half> addrspace(1)* %tmp2, align 4
+ ret void
+}
+
+; GCN-LABEL: {{^}}test_pk_max_f16_literal_0_m1:
+; GFX9: v_pk_max_f16 v{{[0-9]+}}, -1.0, v{{[0-9]+}} op_sel:[1,0] op_sel_hi:[0,1]{{$}}
+define amdgpu_kernel void @test_pk_max_f16_literal_0_m1(<2 x half> addrspace(1)* nocapture %arg) {
+bb:
+ %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
+ %tmp1 = zext i32 %tmp to i64
+ %tmp2 = getelementptr inbounds <2 x half>, <2 x half> addrspace(1)* %arg, i64 %tmp1
+ %tmp3 = load <2 x half>, <2 x half> addrspace(1)* %tmp2, align 4
+ %tmp4 = tail call <2 x half> @llvm.maxnum.v2f16(<2 x half> %tmp3, <2 x half> <half 0xH0000, half 0xHBC00>)
+ store <2 x half> %tmp4, <2 x half> addrspace(1)* %tmp2, align 4
+ ret void
+}
+
+; GCN-LABEL: {{^}}test_pk_max_f16_literal_m1_0:
+; GFX9: v_pk_max_f16 v{{[0-9]+}}, v{{[0-9]+}}, -1.0{{$}}
+define amdgpu_kernel void @test_pk_max_f16_literal_m1_0(<2 x half> addrspace(1)* nocapture %arg) {
+bb:
+ %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
+ %tmp1 = zext i32 %tmp to i64
+ %tmp2 = getelementptr inbounds <2 x half>, <2 x half> addrspace(1)* %arg, i64 %tmp1
+ %tmp3 = load <2 x half>, <2 x half> addrspace(1)* %tmp2, align 4
+ %tmp4 = tail call <2 x half> @llvm.maxnum.v2f16(<2 x half> %tmp3, <2 x half> <half 0xHBC00, half 0xH0000>)
+ store <2 x half> %tmp4, <2 x half> addrspace(1)* %tmp2, align 4
+ ret void
+}
+
+; GCN-LABEL: {{^}}test_pk_max_f16_literal_m1_m1:
+; GFX9: v_pk_max_f16 v{{[0-9]+}}, v{{[0-9]+}}, -1.0 op_sel_hi:[1,0]{{$}}
+define amdgpu_kernel void @test_pk_max_f16_literal_m1_m1(<2 x half> addrspace(1)* nocapture %arg) {
+bb:
+ %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
+ %tmp1 = zext i32 %tmp to i64
+ %tmp2 = getelementptr inbounds <2 x half>, <2 x half> addrspace(1)* %arg, i64 %tmp1
+ %tmp3 = load <2 x half>, <2 x half> addrspace(1)* %tmp2, align 4
+ %tmp4 = tail call <2 x half> @llvm.maxnum.v2f16(<2 x half> %tmp3, <2 x half> <half 0xHBC00, half 0xHBC00>)
+ store <2 x half> %tmp4, <2 x half> addrspace(1)* %tmp2, align 4
+ ret void
+}
+
+; GCN-LABEL: {{^}}test_pk_max_f16_literal_0_0:
+; GFX9: v_pk_max_f16 v{{[0-9]+}}, v{{[0-9]+}}, 0{{$}}
+define amdgpu_kernel void @test_pk_max_f16_literal_0_0(<2 x half> addrspace(1)* nocapture %arg) {
+bb:
+ %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
+ %tmp1 = zext i32 %tmp to i64
+ %tmp2 = getelementptr inbounds <2 x half>, <2 x half> addrspace(1)* %arg, i64 %tmp1
+ %tmp3 = load <2 x half>, <2 x half> addrspace(1)* %tmp2, align 4
+ %tmp4 = tail call <2 x half> @llvm.maxnum.v2f16(<2 x half> %tmp3, <2 x half> <half 0xH0000, half 0xH0000>)
+ store <2 x half> %tmp4, <2 x half> addrspace(1)* %tmp2, align 4
+ ret void
+}
+
+declare <2 x half> @llvm.maxnum.v2f16(<2 x half>, <2 x half>)
+declare i32 @llvm.amdgcn.workitem.id.x()
Modified: llvm/trunk/test/CodeGen/AMDGPU/sub.v2i16.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/sub.v2i16.ll?rev=330365&r1=330364&r2=330365&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/sub.v2i16.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/sub.v2i16.ll Thu Apr 19 14:16:50 2018
@@ -112,8 +112,7 @@ define amdgpu_kernel void @v_test_sub_v2
}
; GCN-LABEL: {{^}}v_test_sub_v2i16_inline_lo_zero_hi:
-; GFX9: s_mov_b32 [[K:s[0-9]+]], 32{{$}}
-; GFX9: v_pk_sub_i16 v{{[0-9]+}}, v{{[0-9]+}}, [[K]]
+; GFX9: v_pk_sub_i16 v{{[0-9]+}}, v{{[0-9]+}}, 32{{$}}
; VI-NOT: v_subrev_i16
; VI: v_add_u16_e32 v{{[0-9]+}}, 0xffffffe0, v{{[0-9]+}}
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