[PATCH] D45821: [AArch64] improve code generation of vectors smaller than 64 bit

[Eli Friedman via Phabricator via llvm-commits]

efriedma added a comment.

I'm fine with this; AArch64 supports mostly the same operations at bitwidth 8/16/32.



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Comment at: llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp:618
-    // We scalarize the loads/stores because there is not v.4b register and we
-    // have to promote the elements to v.4h.
-    unsigned NumVecElts = Ty->getVectorNumElements();
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We could fix this even if we don't widen vectors; just need to add a custom lowering.


https://reviews.llvm.org/D45821