[PATCH] D45690: [AArch64][SVE] Asm: Support for contiguous LD1 (scalar+scalar) load instructions.

Florian Hahn via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Thu Apr 19 07:32:11 PDT 2018

Previous message: [PATCH] D45690: [AArch64][SVE] Asm: Support for contiguous LD1 (scalar+scalar) load instructions.
Next message: [PATCH] D45690: [AArch64][SVE] Asm: Support for contiguous LD1 (scalar+scalar) load instructions.
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

fhahn accepted this revision.
fhahn added a comment.
This revision is now accepted and ready to land.

LGTM, mechanical change adding support for SVE  LD1 (scalar+scalar) instrucitons


https://reviews.llvm.org/D45690

Previous message: [PATCH] D45690: [AArch64][SVE] Asm: Support for contiguous LD1 (scalar+scalar) load instructions.
Next message: [PATCH] D45690: [AArch64][SVE] Asm: Support for contiguous LD1 (scalar+scalar) load instructions.
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

More information about the llvm-commits mailing list