[PATCH] D45522: [PowerPC] fix incorrect vectorization of abs() on POWER9

[Nemanja Ivanovic via Phabricator via llvm-commits]

nemanjai added a comment.

Sorry, I find the code kind of difficult to follow now. This is exacerbated by the fact that we end up creating nodes with `AddOpcode` that produce unary operations - which is very counter intuitive. I think it would be much easier to follow if you made it flow more naturally. Perhaps something along the lines of:

  MachineSDNode *flipSign(...)
    if (Type == v4i32)
      <produce and return XVNEGSP>
    if (Type == v8i16)
      <produce the { 0x8000, 0x8000, ... } vector> // The implicit CSE in the DAG will ensure we don't get multiple nodes
    else if (Type == v16i8)
      <produce the { 0x80, 0x80, ... } vector>     // The implicit CSE in the DAG will ensure we don't get multiple nodes
    if (InputOp == Zero)
      <return vector from above>
  
    <produce and return the add/xor>
  ...
  if (SkipAdjust)
    <just produce VABSDU[BHW], replace, return>
  if (Opcode == SUB)
    Op1 = flipSign(Operand1)
    Op2 = flipSign(Operand2)
  else
    Op1 = flipSign(Operand1)
    Op2 = flipSign(Zero)
  <produce VABSDU[BHW] with Op1/Op2, replace, return>

I think that if it's structured in a similar way, it is much easier to follow the code and see exactly what is going on.


https://reviews.llvm.org/D45522