[llvm] r330318 - [X86][BtVer2] Remove 128-bit F16C InstRW overrides.

[Simon Pilgrim via llvm-commits]

Author: rksimon
Date: Thu Apr 19 04:16:33 2018
New Revision: 330318

URL: http://llvm.org/viewvc/llvm-project?rev=330318&view=rev
Log:
[X86][BtVer2] Remove 128-bit F16C InstRW overrides.

These are already handled identically by WriteCvtF2F.

Modified:
    llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td

Modified: llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td?rev=330318&r1=330317&r2=330318&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td (original)
+++ llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td Thu Apr 19 04:16:33 2018
@@ -502,21 +502,11 @@ def : InstRW<[JWriteINSERTQ], (instrs IN
 // F16C instructions.
 ////////////////////////////////////////////////////////////////////////////////
 
-def JWriteCVT3: SchedWriteRes<[JFPU1, JSTC]> {
-  let Latency = 3;
-}
-def : InstRW<[JWriteCVT3], (instrs VCVTPS2PHrr, VCVTPH2PSrr)>;
-
 def JWriteCVT3St: SchedWriteRes<[JFPU1, JSTC, JSAGU]> {
   let Latency = 3;
 }
 def : InstRW<[JWriteCVT3St], (instrs VCVTPS2PHmr)>;
 
-def JWriteCVT3Ld: SchedWriteRes<[JLAGU, JFPU1, JSTC]> {
-  let Latency = 8;
-}
-def : InstRW<[JWriteCVT3Ld], (instrs VCVTPH2PSrm)>;
-
 def JWriteCVTPS2PHY: SchedWriteRes<[JFPU1, JSTC, JFPX]> {
   let Latency = 6;
   let ResourceCycles = [2, 2, 2];