[PATCH] D33312: [Sparc] Support calls to absolute addresses

[Daniel Cederman via Phabricator via llvm-commits]

dcederman updated this revision to Diff 142905.
dcederman retitled this revision from "[Sparc] Do not encode the 2 LSBs of the address in the call instruction" to "[Sparc] Support calls to absolute addresses".
dcederman edited the summary of this revision.

https://reviews.llvm.org/D33312

Files:
  lib/Target/Sparc/InstPrinter/SparcInstPrinter.cpp
  lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp
  test/MC/Disassembler/Sparc/sparc.txt
  test/MC/Sparc/sparc-ctrl-instructions.s


Index: test/MC/Sparc/sparc-ctrl-instructions.s
===================================================================
--- test/MC/Sparc/sparc-ctrl-instructions.s
+++ test/MC/Sparc/sparc-ctrl-instructions.s
@@ -14,6 +14,10 @@
         ! CHECK: call %g1     ! encoding: [0x9f,0xc0,0x40,0x00]
         call %g1
 
+        ! CHECK: call 0x40000000   ! encoding: [0b01AAAAAA,A,A,A]
+              ! fixup A - offset: 0, value: 1073741824, kind: fixup_sparc_call30
+        call 0x40000000
+
         ! CHECK: call %g1+%lo(sym)   ! encoding: [0x9f,0xc0,0b011000AA,A]
         ! CHECK-NEXT:                ! fixup A - offset: 0, value: %lo(sym), kind: fixup_sparc_lo10
         call %g1+%lo(sym)
Index: test/MC/Disassembler/Sparc/sparc.txt
===================================================================
--- test/MC/Disassembler/Sparc/sparc.txt
+++ test/MC/Disassembler/Sparc/sparc.txt
@@ -216,7 +216,7 @@
 # CHECK: restore
 0x81 0xe8 0x00 0x00
 
-# CHECK: call 16
+# CHECK: call 0x10
 0x40 0x00 0x00 0x04
 
 # CHECK: add %g1, -10, %g2
Index: lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp
===================================================================
--- lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp
+++ lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp
@@ -156,7 +156,7 @@
                      SmallVectorImpl<MCFixup> &Fixups,
                      const MCSubtargetInfo &STI) const {
   const MCOperand &MO = MI.getOperand(OpNo);
-  if (MO.isReg() || MO.isImm())
+  if (MO.isReg())
     return getMachineOpValue(MI, MO, Fixups, STI);
 
   if (MI.getOpcode() == SP::TLS_CALL) {
@@ -176,6 +176,12 @@
 
   MCFixupKind fixupKind = (MCFixupKind)Sparc::fixup_sparc_call30;
 
+  if (MO.isImm()) {
+    Fixups.push_back(MCFixup::create(
+        0, MCConstantExpr::create(MO.getImm(), Ctx), fixupKind));
+    return 0;
+  }
+
   if (const SparcMCExpr *SExpr = dyn_cast<SparcMCExpr>(MO.getExpr())) {
     if (SExpr->getKind() == SparcMCExpr::VK_Sparc_WPLT30)
       fixupKind = (MCFixupKind)Sparc::fixup_sparc_wplt30;
Index: lib/Target/Sparc/InstPrinter/SparcInstPrinter.cpp
===================================================================
--- lib/Target/Sparc/InstPrinter/SparcInstPrinter.cpp
+++ lib/Target/Sparc/InstPrinter/SparcInstPrinter.cpp
@@ -120,7 +120,10 @@
       default:
         O << (int)MO.getImm(); 
         return;
-        
+      case SP::CALL:
+        O << "0x";
+        O.write_hex(MO.getImm());
+        return;
       case SP::TICCri: // Fall through
       case SP::TICCrr: // Fall through
       case SP::TRAPri: // Fall through


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