[PATCH] D45732: [GlobalISel] Making VRegs w/ LLTs and RegClasses both illegal

Roman Tereshin via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Tue Apr 17 11:49:23 PDT 2018


rtereshin created this revision.
rtereshin added reviewers: aditya_nandakumar, volkan, dsanders, bogner.
Herald added subscribers: javed.absar, kristof.beyls, rovka, mehdi_amini.

anywhere but mid-InstructionSelect pass.

The rationale behind this is the consideration that dealing w/
instructions that def/use VRegs each of which could be in one of the 3
configurations:

a) LLT (optional RegBank)
b) RegClass
c) LLT and RegClass both

throughout the GlobalISel is getting tedious and error-prone very
quickly as the number of VRegs def/used increases, and it's better to
forbid the config (c) altogether to simplify the implementation and
decrease the number of hidden bugs. Apparently, the GlobalISel
implementation already assumes that in a few places, this decision was
made a while ago, but it was never actually enforced.

This commit explicitly enforces the invariant at passes' boundaries
with MachineVerifier, and implicitly intra-pass except
InstructionSelect, which is expected to introduce such VRegs for
performance reasons, as the pass eliminates LLTs by the end of it
anyway.

This patch also tries its best to fix all the failures that came out
of it. The most affected parts are:

1. CallLowering: lowering ABI naturally introduces a few selected MIR / non-selected MIR boundaries, which many targets shaped with LLT + RegClass VRegs, now illegal.

2. selectCopy: as GlobalISel doesn't supply tools for assigning RegClasses during selection to def/uses of COPYs, this is done by every target independently in a very similar manner with common drawbacks, e.g. assuming that SRC-vreg of a COPY could not have (meaningful) RegClass attached and whatnot. As the number of COPYs between typed and regclassed VRegs increases with this commit, some of these issues got exposed and had to be fixed to the best of my understanding of the target-specific implementation.

3. constrainOperandRegClass set of GlobalISel utils, apparently promising but not delivering auto-COPY-insertion for defs, not just uses was fixed as well and updated in a way that should make it easier to migrate legalizer-implementations and other parts of non-upstream targets.

This is related to, but not dependent on https://reviews.llvm.org/D45644 and https://reviews.llvm.org/D45640


Repository:
  rL LLVM

https://reviews.llvm.org/D45732

Files:
  include/llvm/CodeGen/GlobalISel/Utils.h
  include/llvm/CodeGen/MachineInstrBuilder.h
  include/llvm/CodeGen/MachineOperand.h
  lib/CodeGen/GlobalISel/IRTranslator.cpp
  lib/CodeGen/GlobalISel/InstructionSelector.cpp
  lib/CodeGen/GlobalISel/Utils.cpp
  lib/CodeGen/MachineOperand.cpp
  lib/CodeGen/MachineVerifier.cpp
  lib/Target/AArch64/AArch64CallLowering.cpp
  lib/Target/AArch64/AArch64InstructionSelector.cpp
  lib/Target/ARM/ARMCallLowering.cpp
  lib/Target/ARM/ARMInstructionSelector.cpp
  lib/Target/X86/X86CallLowering.cpp
  lib/Target/X86/X86InstructionSelector.cpp
  test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-stackprotect.ll
  test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir
  test/CodeGen/AArch64/GlobalISel/call-translator.ll
  test/CodeGen/AArch64/GlobalISel/irtranslator-exceptions.ll
  test/CodeGen/AArch64/GlobalISel/select-copy.ll
  test/CodeGen/ARM/GlobalISel/arm-call-lowering.ll
  test/CodeGen/X86/GlobalISel/irtranslator-callingconv.ll

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