[PATCH] D45563: [X86][AArch64][NFC] Add tests for masked merge unfolding

[Sanjay Patel via Phabricator via llvm-commits]

spatel added a comment.

In https://reviews.llvm.org/D45563#1069968, @nemanjai wrote:

> In https://reviews.llvm.org/D45563#1069916, @spatel wrote:
>
> >
>
>
> Not sure this answer is pertinent any longer, but on PPC we can generate the VSX version of the vector select (`xxsel`) for rather specific situations. See `test/CodeGen/PowerPC/vselect-constants.ll` and `test/CodeGen/PowerPC/vsx.ll`.


I think it's still valid. Didn't mean to be cryptic - here's the vector example from this patch compiled for PPC64le:

  define <4 x i32> @out_vec(<4 x i32> %x, <4 x i32> %y, <4 x i32> %mask) {
    %mx = and <4 x i32> %x, %mask
    %notmask = xor <4 x i32> %mask, <i32 -1, i32 -1, i32 -1, i32 -1>
    %my = and <4 x i32> %y, %notmask
    %r = or <4 x i32> %mx, %my
    ret <4 x i32> %r
  }

$ ./llc -o - vsel.ll -mtriple=powerpc64le
	xxland 0, 34, 36
	xxlandc 1, 35, 36
	xxlor 34, 0, 1
blr

xxsel 0, 35, 34, 36 ?


Repository:
  rL LLVM

https://reviews.llvm.org/D45563