[PATCH] D45651: [X86] Add DAG combine to turn (trunc (srl (mul ext, ext), 16) into PMULHW/PMULHUW.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

I thought about that. But it needs to be done pre-type legalization so that the extends haven’t been legalized yet. And it needs to be done on wider than legal vectors so the MULHU/MULHS get split during type legalization.

I think this means a generic DAG combine couldnt check isOperationLegal. Which sounds fine at first, but if the VT ends up needing to be promoted we’ll crash because type promotion doesn’t know how to promote MULHS/MULHU. So I wasn’t sure how to cleanly protect that from DAG combine.


Repository:
  rL LLVM

https://reviews.llvm.org/D45651