[llvm] r330021 - Remove comment references to itineraries. NFCI.

[Simon Pilgrim via llvm-commits]

Author: rksimon
Date: Fri Apr 13 07:31:57 2018
New Revision: 330021

URL: http://llvm.org/viewvc/llvm-project?rev=330021&view=rev
Log:
Remove comment references to itineraries. NFCI.

Modified:
    llvm/trunk/lib/Target/X86/X86InstrMPX.td
    llvm/trunk/lib/Target/X86/X86Schedule.td
    llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td

Modified: llvm/trunk/lib/Target/X86/X86InstrMPX.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrMPX.td?rev=330021&r1=330020&r2=330021&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrMPX.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrMPX.td Fri Apr 13 07:31:57 2018
@@ -13,7 +13,7 @@
 //
 //===----------------------------------------------------------------------===//
 
-// FIXME: Investigate a better scheduler itinerary once MPX is used inside LLVM.
+// FIXME: Investigate a better scheduler class once MPX is used inside LLVM.
 let SchedRW = [WriteSystem] in {
 
 multiclass mpx_bound_make<bits<8> opc, string OpcodeStr> {

Modified: llvm/trunk/lib/Target/X86/X86Schedule.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Schedule.td?rev=330021&r1=330020&r2=330021&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86Schedule.td (original)
+++ llvm/trunk/lib/Target/X86/X86Schedule.td Fri Apr 13 07:31:57 2018
@@ -183,7 +183,7 @@ def WriteNop : SchedWrite;
 // latencies. Since these latencies are not used for pipeline hazards,
 // they do not need to be exact.
 //
-// The GenericX86Model contains no instruction itineraries
+// The GenericX86Model contains no instruction schedules
 // and disables PostRAScheduler.
 class GenericX86Model : SchedMachineModel {
   let IssueWidth = 4;

Modified: llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td?rev=330021&r1=330020&r2=330021&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td (original)
+++ llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td Fri Apr 13 07:31:57 2018
@@ -246,7 +246,7 @@ def : WriteRes<WriteNop, []>;
 defm : ZnWriteResFpuPair<WriteFShuffle256, [ZnFPU], 100>;
 defm : ZnWriteResFpuPair<WriteFVarShuffle256, [ZnFPU], 100>;
 
-//Microcoded Instructions
+// Microcoded Instructions
 let Latency = 100 in {
   def : WriteRes<WriteMicrocoded, []>;
   def : WriteRes<WriteSystem, []>;
@@ -264,7 +264,7 @@ let Latency = 100 in {
   def : WriteRes<WritePCmpIStrILd, []>;
   }
 
-//=== Regex based itineraries ===//
+//=== Regex based InstRW ===//
 // Notation:
 // - r: register.
 // - m = memory.