[PATCH] D45618: [AArch64][SVE] Asm: Support for contiguous LD1 (scalar+imm) load instructions

[Renato Golin via Phabricator via llvm-commits]

rengolin added inline comments.


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Comment at: lib/Target/AArch64/AArch64SVEInstrInfo.td:32
+  defm LD1H_D_IMM  : sve_mem_cld_si<0b0111, "ld1h",  Z_d, ZPR64>;
+  defm LD1SH_D_IMM : sve_mem_cld_si<0b1000, "ld1sh", Z_d, ZPR64>;
+  defm LD1SH_S_IMM : sve_mem_cld_si<0b1001, "ld1sh", Z_s, ZPR32>;
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sdesmalen wrote:
> rengolin wrote:
> > Nit: keep the same order S/D :)
> I actually did this on purpose because the SVE specification orders it by encoding (first column).
makes sense. As good reason as any. :)


https://reviews.llvm.org/D45618