[llvm] r330006 - [NFC] fix trivial typos in comments
Hiroshi Inoue via llvm-commits
llvm-commits at lists.llvm.org
Fri Apr 13 04:37:06 PDT 2018
Author: inouehrs
Date: Fri Apr 13 04:37:06 2018
New Revision: 330006
URL: http://llvm.org/viewvc/llvm-project?rev=330006&view=rev
Log:
[NFC] fix trivial typos in comments
"the the" -> "the", "we we" -> "we", etc
Modified:
llvm/trunk/include/llvm/Support/CrashRecoveryContext.h
llvm/trunk/include/llvm/Support/Unicode.h
llvm/trunk/lib/CodeGen/MachinePipeliner.cpp
llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp
llvm/trunk/lib/Target/AMDGPU/SIShrinkInstructions.cpp
llvm/trunk/lib/Target/Hexagon/HexagonNewValueJump.cpp
llvm/trunk/lib/Target/X86/X86FlagsCopyLowering.cpp
llvm/trunk/test/CodeGen/SPARC/vector-extract-elt.ll
llvm/trunk/test/CodeGen/X86/pr29010.ll
Modified: llvm/trunk/include/llvm/Support/CrashRecoveryContext.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/CrashRecoveryContext.h?rev=330006&r1=330005&r2=330006&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Support/CrashRecoveryContext.h (original)
+++ llvm/trunk/include/llvm/Support/CrashRecoveryContext.h Fri Apr 13 04:37:06 2018
@@ -54,7 +54,7 @@ public:
/// Register cleanup handler, which is used when the recovery context is
/// finished.
- /// The recovery context owns the the handler.
+ /// The recovery context owns the handler.
void registerCleanup(CrashRecoveryContextCleanup *cleanup);
void unregisterCleanup(CrashRecoveryContextCleanup *cleanup);
Modified: llvm/trunk/include/llvm/Support/Unicode.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/Unicode.h?rev=330006&r1=330005&r2=330006&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Support/Unicode.h (original)
+++ llvm/trunk/include/llvm/Support/Unicode.h Fri Apr 13 04:37:06 2018
@@ -60,7 +60,7 @@ bool isPrintable(int UCS);
/// * 1 for each of the remaining characters.
int columnWidthUTF8(StringRef Text);
-/// Fold input unicode character according the the Simple unicode case folding
+/// Fold input unicode character according the Simple unicode case folding
/// rules.
int foldCharSimple(int C);
Modified: llvm/trunk/lib/CodeGen/MachinePipeliner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachinePipeliner.cpp?rev=330006&r1=330005&r2=330006&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachinePipeliner.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachinePipeliner.cpp Fri Apr 13 04:37:06 2018
@@ -1991,7 +1991,7 @@ void SwingSchedulerDAG::groupRemainingNo
if (!NewSet.empty())
NodeSets.push_back(NewSet);
- // Create new nodes sets with the connected nodes any any remaining node that
+ // Create new nodes sets with the connected nodes any remaining node that
// has no predecessor.
for (unsigned i = 0; i < SUnits.size(); ++i) {
SUnit *SU = &SUnits[i];
Modified: llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp?rev=330006&r1=330005&r2=330006&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp Fri Apr 13 04:37:06 2018
@@ -4188,7 +4188,7 @@ SDValue SITargetLowering::lowerEXTRACT_V
DAGCombinerInfo DCI(DAG, AfterLegalizeVectorOps, true, nullptr);
- // Make sure we we do any optimizations that will make it easier to fold
+ // Make sure we do any optimizations that will make it easier to fold
// source modifiers before obscuring it with bit operations.
// XXX - Why doesn't this get called when vector_shuffle is expanded?
Modified: llvm/trunk/lib/Target/AMDGPU/SIShrinkInstructions.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIShrinkInstructions.cpp?rev=330006&r1=330005&r2=330006&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIShrinkInstructions.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIShrinkInstructions.cpp Fri Apr 13 04:37:06 2018
@@ -443,7 +443,7 @@ bool SIShrinkInstructions::runOnMachineF
// VCC, e.g. S_AND_B64 (vcc = V_CMP_...), (vcc = V_CMP_...)
//
// So, instead of forcing the instruction to write to VCC, we provide
- // a hint to the register allocator to use VCC and then we we will run
+ // a hint to the register allocator to use VCC and then we will run
// this pass again after RA and shrink it if it outputs to VCC.
MRI.setRegAllocationHint(MI.getOperand(0).getReg(), 0, AMDGPU::VCC);
continue;
Modified: llvm/trunk/lib/Target/Hexagon/HexagonNewValueJump.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonNewValueJump.cpp?rev=330006&r1=330005&r2=330006&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonNewValueJump.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonNewValueJump.cpp Fri Apr 13 04:37:06 2018
@@ -522,7 +522,7 @@ bool HexagonNewValueJump::runOnMachineFu
// operands, the following check on the kill flag would suffice.
// if(!jmpInstr->getOperand(0).isKill()) break;
- // This predicate register is live out out of BB
+ // This predicate register is live out of BB
// this would only work if we can actually use Live
// variable analysis on phy regs - but LLVM does not
// provide LV analysis on phys regs.
Modified: llvm/trunk/lib/Target/X86/X86FlagsCopyLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FlagsCopyLowering.cpp?rev=330006&r1=330005&r2=330006&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86FlagsCopyLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86FlagsCopyLowering.cpp Fri Apr 13 04:37:06 2018
@@ -707,7 +707,7 @@ void X86FlagsCopyLoweringPass::rewriteCo
void X86FlagsCopyLoweringPass::rewriteCopy(MachineInstr &MI,
MachineOperand &FlagUse,
MachineInstr &CopyDefI) {
- // Just replace this copy with the the original copy def.
+ // Just replace this copy with the original copy def.
MRI->replaceRegWith(MI.getOperand(0).getReg(),
CopyDefI.getOperand(0).getReg());
MI.eraseFromParent();
Modified: llvm/trunk/test/CodeGen/SPARC/vector-extract-elt.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SPARC/vector-extract-elt.ll?rev=330006&r1=330005&r2=330006&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SPARC/vector-extract-elt.ll (original)
+++ llvm/trunk/test/CodeGen/SPARC/vector-extract-elt.ll Fri Apr 13 04:37:06 2018
@@ -2,7 +2,7 @@
; If computeKnownSignBits (in SelectionDAG) can do a simple
-; look-thru for extractelement then we we know that the add will yield a
+; look-thru for extractelement then we know that the add will yield a
; non-negative result.
define i1 @test1(<4 x i16>* %in) {
; CHECK-LABEL: ! %bb.0:
Modified: llvm/trunk/test/CodeGen/X86/pr29010.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr29010.ll?rev=330006&r1=330005&r2=330006&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/pr29010.ll (original)
+++ llvm/trunk/test/CodeGen/X86/pr29010.ll Fri Apr 13 04:37:06 2018
@@ -1,6 +1,6 @@
; RUN: llc < %s -mtriple=i386-linux -mattr=+avx | FileCheck %s
-; In i386 there are only 8 XMMs (xmm0-xmm7), make sure we we are not creating illegal XMM
+; In i386 there are only 8 XMMs (xmm0-xmm7), make sure we are not creating illegal XMM
define float @only_xmm0_7(i32 %arg) {
top:
tail call void asm sideeffect "", "~{xmm0},~{xmm1},~{xmm2},~{xmm3},~{dirflag},~{fpsr},~{flags}"()
More information about the llvm-commits
mailing list