[llvm] r329939 - [RISCV] Add c.mv rs1, rs2 pattern for addi rs1, rs2, 0

[Sameer AbuAsal via llvm-commits]

Author: sabuasal
Date: Thu Apr 12 12:22:40 2018
New Revision: 329939

URL: http://llvm.org/viewvc/llvm-project?rev=329939&view=rev
Log:
[RISCV] Add c.mv rs1, rs2 pattern for addi rs1, rs2, 0

Summary:
GCC compresses the pseudo instruction "mv rd, rs",  which is an alias of
"addi rd, rs, 0", to "c.mv rd, rs".

In LLVM we rely on the canonical MC instruction (MCInst) to do our compression
checks and since there is no rule to compress "addi rd, rs, 0" --> "c.mv
rd, rs" we lose this compression opportunity to gcc.

 In this patch we fix that by adding an addi to c.mv compression pattern, the
 instruction "mv rd, rs" will be compressed to "c.mv rd, rs" just like
 gcc does.

Patch by Zhaoshi Zheng (zzheng) and Sameer (sabuasal).

Reviewers: asb, apazos, zzheng, mgrang, shiva0217

Reviewed By: asb

Subscribers: rbar, johnrusso, simoncook, jordy.potman.lists, niosHD, kito-cheng, llvm-commits

Differential Revision: https://reviews.llvm.org/D45583

Modified:
    llvm/trunk/lib/Target/RISCV/RISCVInstrInfoC.td
    llvm/trunk/test/MC/RISCV/compress-rv32i.s

Modified: llvm/trunk/lib/Target/RISCV/RISCVInstrInfoC.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/RISCV/RISCVInstrInfoC.td?rev=329939&r1=329938&r2=329939&view=diff
==============================================================================
--- llvm/trunk/lib/Target/RISCV/RISCVInstrInfoC.td (original)
+++ llvm/trunk/lib/Target/RISCV/RISCVInstrInfoC.td Thu Apr 12 12:22:40 2018
@@ -675,6 +675,8 @@ def : CompressPat<(ADD GPRNoX0:$rs1, X0,
                   (C_MV GPRNoX0:$rs1, GPRNoX0:$rs2)>;
 def : CompressPat<(ADD GPRNoX0:$rs1, GPRNoX0:$rs2, X0),
                   (C_MV GPRNoX0:$rs1, GPRNoX0:$rs2)>;
+def : CompressPat<(ADDI GPRNoX0:$rs1, GPRNoX0:$rs2, 0),
+                  (C_MV GPRNoX0:$rs1, GPRNoX0:$rs2)>;
 def : CompressPat<(EBREAK), (C_EBREAK)>;
 def : CompressPat<(JALR X1, GPRNoX0:$rs1, 0),
                   (C_JALR GPRNoX0:$rs1)>;

Modified: llvm/trunk/test/MC/RISCV/compress-rv32i.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/RISCV/compress-rv32i.s?rev=329939&r1=329938&r2=329939&view=diff
==============================================================================
--- llvm/trunk/test/MC/RISCV/compress-rv32i.s (original)
+++ llvm/trunk/test/MC/RISCV/compress-rv32i.s Thu Apr 12 12:22:40 2018
@@ -20,6 +20,12 @@
 # RUN: | llvm-objdump  -triple riscv64 -mattr=+c -d -riscv-no-aliases - \
 # RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-INST %s
 
+# CHECK-BYTES: 2e 85
+# CHECK-ALIAS: add a0, zero, a1
+# CHECK-INST: c.mv a0, a1
+# CHECK: # encoding:  [0x2e,0x85]
+addi a0, a1, 0
+
 # CHECK-BYTES: e0 1f
 # CHECK-ALIAS: addi s0, sp, 1020
 # CHECK-INST: c.addi4spn s0, sp, 1020