[llvm] r329967 - [X86] Remove x86 InstrItinClass entries (PR37093)
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Thu Apr 12 15:44:47 PDT 2018
Author: rksimon
Date: Thu Apr 12 15:44:47 2018
New Revision: 329967
URL: http://llvm.org/viewvc/llvm-project?rev=329967&view=rev
Log:
[X86] Remove x86 InstrItinClass entries (PR37093)
This removes the last of the x86 schedule itineraries, I'm intending to cleanup the remaining uses of NoItinerary/OpndItins/etc. before resolving PR37093.
Modified:
llvm/trunk/lib/Target/X86/X86InstrAVX512.td
llvm/trunk/lib/Target/X86/X86InstrSSE.td
llvm/trunk/lib/Target/X86/X86Schedule.td
Modified: llvm/trunk/lib/Target/X86/X86InstrAVX512.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrAVX512.td?rev=329967&r1=329966&r2=329967&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrAVX512.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrAVX512.td Thu Apr 12 15:44:47 2018
@@ -585,11 +585,11 @@ multiclass vinsert_for_type<ValueType El
// FIXME: Is there a better scheduler itinerary for VINSERTF/VINSERTI?
let Sched = WriteFShuffle256 in
def AVX512_VINSERTF : OpndItins<
- IIC_SSE_SHUFP, IIC_SSE_SHUFP
+ NoItinerary, NoItinerary
>;
let Sched = WriteShuffle256 in
def AVX512_VINSERTI : OpndItins<
- IIC_SSE_PSHUF_RI, IIC_SSE_PSHUF_MI
+ NoItinerary, NoItinerary
>;
defm VINSERTF : vinsert_for_type<f32, 0x18, f64, 0x1a, AVX512_VINSERTF>;
@@ -1712,12 +1712,12 @@ defm VPBROADCASTMB2Q : avx512_mask_broad
let Sched = WriteFVarShuffle256 in
def AVX512_PERM2_F : OpndItins<
- IIC_SSE_SHUFP, IIC_SSE_SHUFP
+ NoItinerary, NoItinerary
>;
let Sched = WriteVarShuffle256 in
def AVX512_PERM2_I : OpndItins<
- IIC_SSE_PSHUF_RI, IIC_SSE_PSHUF_MI
+ NoItinerary, NoItinerary
>;
multiclass avx512_perm_i<bits<8> opc, string OpcodeStr, OpndItins itins,
@@ -1881,12 +1881,12 @@ defm VPERMT2PD : avx512_perm_t_sizes<0x7
let Sched = WriteFVarBlend in
def AVX512_BLENDM : OpndItins<
- IIC_SSE_ALU_F32P_RR, IIC_SSE_ALU_F32P_RM
+ NoItinerary, NoItinerary
>;
let Sched = WriteVarBlend in
def AVX512_PBLENDM : OpndItins<
- IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
+ NoItinerary, NoItinerary
>;
multiclass avx512_blendmask<bits<8> opc, string OpcodeStr, OpndItins itins,
@@ -5689,7 +5689,7 @@ multiclass avx512_var_shift_w<bits<8> op
let Sched = WriteVarVecShift in
def AVX512_VARSHIFT_P : OpndItins<
- IIC_SSE_INTSH_P_RR, IIC_SSE_INTSH_P_RM
+ NoItinerary, NoItinerary
>;
defm VPSLLV : avx512_var_shift_types<0x47, "vpsllv", shl, AVX512_VARSHIFT_P>,
@@ -8199,12 +8199,12 @@ defm VRNDSCALESD : avx512_rndscale_scala
let Sched = WriteShuffle256 in
def AVX512_EXTEND : OpndItins<
- IIC_SSE_PSHUF_RI, IIC_SSE_PSHUF_MI
+ NoItinerary, NoItinerary
>;
let Sched = WriteShuffle256 in
def AVX512_TRUNCATE : OpndItins<
- IIC_SSE_PSHUF_RI, IIC_SSE_PSHUF_MI
+ NoItinerary, NoItinerary
>;
multiclass avx512_trunc_common<bits<8> opc, string OpcodeStr, SDNode OpNode,
@@ -8939,10 +8939,10 @@ let Predicates = [HasDQI, NoBWI] in {
// FIXME: Is there a better scheduler itinerary for VPCOMPRESS/VPEXPAND?
let Sched = WriteVarShuffle256 in {
def AVX512_COMPRESS : OpndItins<
- IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
+ NoItinerary, NoItinerary
>;
def AVX512_EXPAND : OpndItins<
- IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
+ NoItinerary, NoItinerary
>;
}
@@ -10035,7 +10035,7 @@ defm VSHUFPD: avx512_shufp<"vshufpd", av
let Sched = WriteVecShift in
def AVX512_BYTESHIFT : OpndItins<
- IIC_SSE_INTSHDQ_P_RI, IIC_SSE_INTSHDQ_P_RI
+ NoItinerary, NoItinerary
>;
multiclass avx512_shift_packed<bits<8> opc, SDNode OpNode, Format MRMr,
Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=329967&r1=329966&r2=329967&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Thu Apr 12 15:44:47 2018
@@ -42,11 +42,11 @@ class ShiftOpndItins<InstrItinClass arg_
// scalar
let Sched = WriteFAdd in {
def SSE_ALU_F32S : OpndItins<
- IIC_SSE_ALU_F32S_RR, IIC_SSE_ALU_F32S_RM
+ NoItinerary, NoItinerary
>;
def SSE_ALU_F64S : OpndItins<
- IIC_SSE_ALU_F64S_RR, IIC_SSE_ALU_F64S_RM
+ NoItinerary, NoItinerary
>;
}
@@ -56,11 +56,11 @@ def SSE_ALU_ITINS_S : SizeItins<
let Sched = WriteFMul in {
def SSE_MUL_F32S : OpndItins<
- IIC_SSE_MUL_F32S_RR, IIC_SSE_MUL_F32S_RM
+ NoItinerary, NoItinerary
>;
def SSE_MUL_F64S : OpndItins<
- IIC_SSE_MUL_F64S_RR, IIC_SSE_MUL_F64S_RM
+ NoItinerary, NoItinerary
>;
}
@@ -70,11 +70,11 @@ def SSE_MUL_ITINS_S : SizeItins<
let Sched = WriteFDiv in {
def SSE_DIV_F32S : OpndItins<
- IIC_SSE_DIV_F32S_RR, IIC_SSE_DIV_F32S_RM
+ NoItinerary, NoItinerary
>;
def SSE_DIV_F64S : OpndItins<
- IIC_SSE_DIV_F64S_RR, IIC_SSE_DIV_F64S_RM
+ NoItinerary, NoItinerary
>;
}
@@ -85,11 +85,11 @@ def SSE_DIV_ITINS_S : SizeItins<
// parallel
let Sched = WriteFAdd in {
def SSE_ALU_F32P : OpndItins<
- IIC_SSE_ALU_F32P_RR, IIC_SSE_ALU_F32P_RM
+ NoItinerary, NoItinerary
>;
def SSE_ALU_F64P : OpndItins<
- IIC_SSE_ALU_F64P_RR, IIC_SSE_ALU_F64P_RM
+ NoItinerary, NoItinerary
>;
}
@@ -99,11 +99,11 @@ def SSE_ALU_ITINS_P : SizeItins<
let Sched = WriteFMul in {
def SSE_MUL_F32P : OpndItins<
- IIC_SSE_MUL_F32P_RR, IIC_SSE_MUL_F32P_RM
+ NoItinerary, NoItinerary
>;
def SSE_MUL_F64P : OpndItins<
- IIC_SSE_MUL_F64P_RR, IIC_SSE_MUL_F64P_RM
+ NoItinerary, NoItinerary
>;
}
@@ -113,11 +113,11 @@ def SSE_MUL_ITINS_P : SizeItins<
let Sched = WriteFDiv in {
def SSE_DIV_F32P : OpndItins<
- IIC_SSE_DIV_F32P_RR, IIC_SSE_DIV_F32P_RM
+ NoItinerary, NoItinerary
>;
def SSE_DIV_F64P : OpndItins<
- IIC_SSE_DIV_F64P_RR, IIC_SSE_DIV_F64P_RM
+ NoItinerary, NoItinerary
>;
}
@@ -127,78 +127,73 @@ def SSE_DIV_ITINS_P : SizeItins<
let Sched = WriteVecLogic in
def SSE_BIT_ITINS_P : OpndItins<
- IIC_SSE_BIT_P_RR, IIC_SSE_BIT_P_RM
+ NoItinerary, NoItinerary
>;
let Sched = WriteVecALU in {
def SSE_INTALU_ITINS_P : OpndItins<
- IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
+ NoItinerary, NoItinerary
>;
def SSE_INTALUQ_ITINS_P : OpndItins<
- IIC_SSE_INTALUQ_P_RR, IIC_SSE_INTALUQ_P_RM
+ NoItinerary, NoItinerary
>;
}
let Sched = WriteVecIMul in
def SSE_INTMUL_ITINS_P : OpndItins<
- IIC_SSE_INTMUL_P_RR, IIC_SSE_INTMUL_P_RM
+ NoItinerary, NoItinerary
>;
-// FIXME: Merge SSE_INTSHIFT_P + SSE_INTSHIFT_ITINS_P.
let Sched = WriteVecShift in
def SSE_INTSHIFT_P : OpndItins<
- IIC_SSE_INTSH_P_RR, IIC_SSE_INTSH_P_RM
->;
-
-def SSE_INTSHIFT_ITINS_P : ShiftOpndItins<
- IIC_SSE_INTSH_P_RR, IIC_SSE_INTSH_P_RM, IIC_SSE_INTSH_P_RI
+ NoItinerary, NoItinerary
>;
def SSE_MOVA_ITINS : OpndItins<
- IIC_SSE_MOVA_P_RR, IIC_SSE_MOVA_P_RM
+ NoItinerary, NoItinerary
>;
def SSE_MOVA : MoveLoadStoreItins<
- IIC_SSE_MOVA_P_RR, IIC_SSE_MOVA_P_RM, IIC_SSE_MOVA_P_MR
+ NoItinerary, NoItinerary, NoItinerary
>;
def SSE_MOVU_ITINS : OpndItins<
- IIC_SSE_MOVU_P_RR, IIC_SSE_MOVU_P_RM
+ NoItinerary, NoItinerary
>;
def SSE_MOVU : MoveLoadStoreItins<
- IIC_SSE_MOVU_P_RR, IIC_SSE_MOVU_P_RM, IIC_SSE_MOVU_P_MR
+ NoItinerary, NoItinerary, NoItinerary
>;
def SSE_DPPD_ITINS : OpndItins<
- IIC_SSE_DPPD_RR, IIC_SSE_DPPD_RM
+ NoItinerary, NoItinerary
>;
def SSE_DPPS_ITINS : OpndItins<
- IIC_SSE_DPPS_RR, IIC_SSE_DPPS_RM
+ NoItinerary, NoItinerary
>;
def DEFAULT_ITINS : OpndItins<
- IIC_ALU_NONMEM, IIC_ALU_MEM
+ NoItinerary, NoItinerary
>;
def SSE_EXTRACT_ITINS : OpndItins<
- IIC_SSE_EXTRACTPS_RR, IIC_SSE_EXTRACTPS_RM
+ NoItinerary, NoItinerary
>;
def SSE_INSERT_ITINS : OpndItins<
- IIC_SSE_INSERTPS_RR, IIC_SSE_INSERTPS_RM
+ NoItinerary, NoItinerary
>;
let Sched = WriteMPSAD in
def SSE_MPSADBW_ITINS : OpndItins<
- IIC_SSE_MPSADBW_RR, IIC_SSE_MPSADBW_RM
+ NoItinerary, NoItinerary
>;
let Sched = WritePMULLD in
def SSE_PMULLD_ITINS : OpndItins<
- IIC_SSE_PMULLD_RR, IIC_SSE_PMULLD_RM
+ NoItinerary, NoItinerary
>;
// Definitions for backward compatibility.
@@ -206,42 +201,42 @@ def SSE_PMULLD_ITINS : OpndItins<
// than the actual scheduling model.
let Sched = WriteShuffle in
def DEFAULT_ITINS_SHUFFLESCHED : OpndItins<
- IIC_ALU_NONMEM, IIC_ALU_MEM
+ NoItinerary, NoItinerary
>;
let Sched = WriteVecIMul in
def DEFAULT_ITINS_VECIMULSCHED : OpndItins<
- IIC_ALU_NONMEM, IIC_ALU_MEM
+ NoItinerary, NoItinerary
>;
let Sched = WriteShuffle in
def SSE_INTALU_ITINS_SHUFF_P : OpndItins<
- IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
+ NoItinerary, NoItinerary
>;
let Sched = WriteShuffle in
def SSE_PACK : OpndItins<
- IIC_SSE_PACK, IIC_SSE_PACK
+ NoItinerary, NoItinerary
>;
let Sched = WriteVarBlend in
def DEFAULT_ITINS_VARBLENDSCHED : OpndItins<
- IIC_ALU_NONMEM, IIC_ALU_MEM
+ NoItinerary, NoItinerary
>;
let Sched = WriteFVarBlend in
def DEFAULT_ITINS_FVARBLENDSCHED : OpndItins<
- IIC_ALU_NONMEM, IIC_ALU_MEM
+ NoItinerary, NoItinerary
>;
let Sched = WriteFBlend in
def SSE_INTALU_ITINS_FBLEND_P : OpndItins<
- IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
+ NoItinerary, NoItinerary
>;
let Sched = WriteBlend in
def SSE_INTALU_ITINS_BLEND_P : OpndItins<
- IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
+ NoItinerary, NoItinerary
>;
//===----------------------------------------------------------------------===//
@@ -1119,68 +1114,68 @@ let Constraints = "$src1 = $dst", AddedC
let Sched = WriteCvtF2I in {
def SSE_CVT_SS2SI_32 : OpndItins<
- IIC_SSE_CVT_SS2SI32_RR, IIC_SSE_CVT_SS2SI32_RM
+ NoItinerary, NoItinerary
>;
let Sched = WriteCvtF2I in
def SSE_CVT_SS2SI_64 : OpndItins<
- IIC_SSE_CVT_SS2SI64_RR, IIC_SSE_CVT_SS2SI64_RM
+ NoItinerary, NoItinerary
>;
def SSE_CVT_SD2SI : OpndItins<
- IIC_SSE_CVT_SD2SI_RR, IIC_SSE_CVT_SD2SI_RM
+ NoItinerary, NoItinerary
>;
def SSE_CVT_PS2I : OpndItins<
- IIC_SSE_CVT_PS_RR, IIC_SSE_CVT_PS_RM
+ NoItinerary, NoItinerary
>;
def SSE_CVT_PD2I : OpndItins<
- IIC_SSE_CVT_PD_RR, IIC_SSE_CVT_PD_RM
+ NoItinerary, NoItinerary
>;
}
let Sched = WriteCvtI2F in {
def SSE_CVT_SI2SS : OpndItins<
- IIC_SSE_CVT_Scalar_RR, IIC_SSE_CVT_Scalar_RM
+ NoItinerary, NoItinerary
>;
def SSE_CVT_SI2SD : OpndItins<
- IIC_SSE_CVT_Scalar_RR, IIC_SSE_CVT_Scalar_RM
+ NoItinerary, NoItinerary
>;
def SSE_CVT_I2PS : OpndItins<
- IIC_SSE_CVT_PS_RR, IIC_SSE_CVT_PS_RM
+ NoItinerary, NoItinerary
>;
def SSE_CVT_I2PD : OpndItins<
- IIC_SSE_CVT_PD_RR, IIC_SSE_CVT_PD_RM
+ NoItinerary, NoItinerary
>;
}
let Sched = WriteCvtF2F in {
def SSE_CVT_SD2SS : OpndItins<
- IIC_SSE_CVT_Scalar_RR, IIC_SSE_CVT_Scalar_RM
+ NoItinerary, NoItinerary
>;
def SSE_CVT_SS2SD : OpndItins<
- IIC_SSE_CVT_Scalar_RR, IIC_SSE_CVT_Scalar_RM
+ NoItinerary, NoItinerary
>;
def SSE_CVT_PD2PS : OpndItins<
- IIC_SSE_CVT_PD_RR, IIC_SSE_CVT_PD_RM
+ NoItinerary, NoItinerary
>;
def SSE_CVT_PS2PD : OpndItins<
- IIC_SSE_CVT_PD_RR, IIC_SSE_CVT_PD_RM
+ NoItinerary, NoItinerary
>;
def SSE_CVT_PH2PS : OpndItins<
- IIC_SSE_CVT_PS_RR, IIC_SSE_CVT_PS_RM
+ NoItinerary, NoItinerary
>;
def SSE_CVT_PS2PH : OpndItins<
- IIC_SSE_CVT_PS_RR, IIC_SSE_CVT_PS_RM
+ NoItinerary, NoItinerary
>;
}
@@ -2120,7 +2115,7 @@ let Predicates = [UseSSE2] in {
let Sched = WriteFAdd in
def SSE_COMIS : OpndItins<
- IIC_SSE_COMIS_RR, IIC_SSE_COMIS_RM
+ NoItinerary, NoItinerary
>;
// sse12_cmp_scalar - sse 1 & 2 compare scalar instructions
@@ -2413,7 +2408,7 @@ let Predicates = [UseSSE1] in {
let Sched = WriteFShuffle in
def SSE_SHUFP : OpndItins<
- IIC_SSE_SHUFP, IIC_SSE_SHUFP
+ NoItinerary, NoItinerary
>;
/// sse12_shuffle - sse 1 & 2 fp shuffle instructions
@@ -2461,7 +2456,7 @@ let Constraints = "$src1 = $dst" in {
let Sched = WriteFShuffle in
def SSE_UNPCK : OpndItins<
- IIC_SSE_UNPCK, IIC_SSE_UNPCK
+ NoItinerary, NoItinerary
>;
/// sse12_unpack_interleave - sse 1 & 2 fp unpack and interleave
@@ -3034,29 +3029,29 @@ defm : scalar_math_f64_patterns<fdiv, "D
let Sched = WriteFSqrt in {
def SSE_SQRTPS : OpndItins<
- IIC_SSE_SQRTPS_RR, IIC_SSE_SQRTPS_RM
+ NoItinerary, NoItinerary
>;
def SSE_SQRTSS : OpndItins<
- IIC_SSE_SQRTSS_RR, IIC_SSE_SQRTSS_RM
+ NoItinerary, NoItinerary
>;
def SSE_SQRTPD : OpndItins<
- IIC_SSE_SQRTPD_RR, IIC_SSE_SQRTPD_RM
+ NoItinerary, NoItinerary
>;
def SSE_SQRTSD : OpndItins<
- IIC_SSE_SQRTSD_RR, IIC_SSE_SQRTSD_RM
+ NoItinerary, NoItinerary
>;
}
let Sched = WriteFRsqrt in {
def SSE_RSQRTPS : OpndItins<
- IIC_SSE_RSQRTPS_RR, IIC_SSE_RSQRTPS_RM
+ NoItinerary, NoItinerary
>;
def SSE_RSQRTSS : OpndItins<
- IIC_SSE_RSQRTSS_RR, IIC_SSE_RSQRTSS_RM
+ NoItinerary, NoItinerary
>;
}
@@ -3070,11 +3065,11 @@ def SSE_RSQRT_S : SizeItins<
let Sched = WriteFRcp in {
def SSE_RCPP : OpndItins<
- IIC_SSE_RCPP_RR, IIC_SSE_RCPP_RM
+ NoItinerary, NoItinerary
>;
def SSE_RCPS : OpndItins<
- IIC_SSE_RCPS_RR, IIC_SSE_RCPS_RM
+ NoItinerary, NoItinerary
>;
}
@@ -3644,7 +3639,7 @@ let Predicates = [HasAVX, NoVLX] in {
let Sched = WriteVecIMul in
def SSE_PMADD : OpndItins<
- IIC_SSE_PMADD, IIC_SSE_PMADD
+ NoItinerary, NoItinerary
>;
let ExeDomain = SSEPackedInt in { // SSE integer instructions
@@ -3873,7 +3868,7 @@ defm PCMPGTD : PDI_binop_all<0x66, "pcmp
let Sched = WriteShuffle in
def SSE_PSHUF : OpndItins<
- IIC_SSE_PSHUF_RI, IIC_SSE_PSHUF_MI
+ NoItinerary, NoItinerary
>;
let ExeDomain = SSEPackedInt in {
@@ -4045,7 +4040,7 @@ let Constraints = "$src1 = $dst" in {
let Sched = WriteShuffle in
def SSE_PUNPCK : OpndItins<
- IIC_SSE_UNPCK, IIC_SSE_UNPCK
+ NoItinerary, NoItinerary
>;
let ExeDomain = SSEPackedInt in {
@@ -4689,7 +4684,7 @@ let Predicates = [UseSSE3] in {
// FIXME: Improve MOVDDUP/BROADCAST reg/mem scheduling itineraries.
let Sched = WriteFShuffle in
def SSE_MOVDDUP : OpndItins<
- IIC_SSE_MOV_LH, IIC_SSE_MOV_LH
+ NoItinerary, NoItinerary
>;
multiclass sse3_replicate_dfp<string OpcodeStr> {
@@ -4813,7 +4808,7 @@ let Constraints = "$src1 = $dst", Predic
let Sched = WriteFHAdd in
def SSE_HADDSUB : OpndItins<
- IIC_SSE_HADDSUB_RR, IIC_SSE_HADDSUB_RM
+ NoItinerary, NoItinerary
>;
// Horizontal ops
@@ -4896,7 +4891,7 @@ let Constraints = "$src1 = $dst" in {
let Sched = WriteVecALU in
def SSE_PABS : OpndItins<
- IIC_SSE_PABS_RR, IIC_SSE_PABS_RM
+ NoItinerary, NoItinerary
>;
/// SS3I_unop_rm_int - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
@@ -4958,26 +4953,26 @@ defm PABSD : SS3I_unop_rm<0x1E, "pabsd",
let Sched = WritePHAdd in {
def SSE_PHADDSUBD : OpndItins<
- IIC_SSE_PHADDSUBD_RR, IIC_SSE_PHADDSUBD_RM
+ NoItinerary, NoItinerary
>;
def SSE_PHADDSUBSW : OpndItins<
- IIC_SSE_PHADDSUBSW_RR, IIC_SSE_PHADDSUBSW_RM
+ NoItinerary, NoItinerary
>;
def SSE_PHADDSUBW : OpndItins<
- IIC_SSE_PHADDSUBW_RR, IIC_SSE_PHADDSUBW_RM
+ NoItinerary, NoItinerary
>;
}
let Sched = WriteVarShuffle in
def SSE_PSHUFB : OpndItins<
- IIC_SSE_PSHUFB_RR, IIC_SSE_PSHUFB_RM
+ NoItinerary, NoItinerary
>;
let Sched = WriteVecALU in
def SSE_PSIGN : OpndItins<
- IIC_SSE_PSIGN_RR, IIC_SSE_PSIGN_RM
+ NoItinerary, NoItinerary
>;
let Sched = WriteVecIMul in
def SSE_PMULHRSW : OpndItins<
- IIC_SSE_PMULHRSW, IIC_SSE_PMULHRSW
+ NoItinerary, NoItinerary
>;
/// SS3I_binop_rm - Simple SSSE3 bin op
@@ -5172,7 +5167,7 @@ defm PMULHRSW : SS3I_binop_rm<0x0B, "
let Sched = WriteShuffle in
def SSE_PALIGN : OpndItins<
- IIC_SSE_PALIGNRR, IIC_SSE_PALIGNRM
+ NoItinerary, NoItinerary
>;
multiclass ssse3_palignr<string asm, ValueType VT, RegisterClass RC,
@@ -5768,11 +5763,11 @@ let Predicates = [UseAVX] in {
//===----------------------------------------------------------------------===//
def SSE_ROUNDPS : OpndItins<
- IIC_SSE_ROUNDPS_REG, IIC_SSE_ROUNDPS_MEM
+ NoItinerary, NoItinerary
>;
def SSE_ROUNDPD : OpndItins<
- IIC_SSE_ROUNDPD_REG, IIC_SSE_ROUNDPD_MEM
+ NoItinerary, NoItinerary
>;
multiclass sse41_fp_unop_p<bits<8> opc, string OpcodeStr,
@@ -6073,7 +6068,7 @@ let Predicates = [UseSSE41] in {
let Sched = WriteVecLogic in
def SSE_PTEST : OpndItins<
- IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
+ NoItinerary, NoItinerary
>;
// ptest instruction we'll lower to this in X86ISelLowering primarily from
@@ -7601,12 +7596,12 @@ defm VMASKMOVPD : avx_movmask_rm<0x2D, 0
let Sched = WriteFVarShuffle in
def AVX_VPERMILV : OpndItins<
- IIC_SSE_SHUFP, IIC_SSE_SHUFP
+ NoItinerary, NoItinerary
>;
let Sched = WriteFShuffle in
def AVX_VPERMIL : OpndItins<
- IIC_SSE_SHUFP, IIC_SSE_SHUFP
+ NoItinerary, NoItinerary
>;
multiclass avx_permil<bits<8> opc_rm, bits<8> opc_rmi, string OpcodeStr,
@@ -8065,12 +8060,12 @@ let Predicates = [HasAVX1Only] in {
let Sched = WriteFShuffle256 in
def AVX2_PERMV_F : OpndItins<
- IIC_SSE_SHUFP, IIC_SSE_SHUFP
+ NoItinerary, NoItinerary
>;
let Sched = WriteShuffle256 in
def AVX2_PERMV_I : OpndItins<
- IIC_SSE_PSHUF_RI, IIC_SSE_PSHUF_MI
+ NoItinerary, NoItinerary
>;
multiclass avx2_perm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
Modified: llvm/trunk/lib/Target/X86/X86Schedule.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Schedule.td?rev=329967&r1=329966&r2=329967&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86Schedule.td (original)
+++ llvm/trunk/lib/Target/X86/X86Schedule.td Thu Apr 12 15:44:47 2018
@@ -167,148 +167,6 @@ def WriteFence : SchedWrite;
def WriteNop : SchedWrite;
//===----------------------------------------------------------------------===//
-// Instruction Itinerary classes used for X86
-def IIC_ALU_MEM : InstrItinClass;
-def IIC_ALU_NONMEM : InstrItinClass;
-
-// SSE scalar/parallel binary operations
-def IIC_SSE_ALU_F32S_RR : InstrItinClass;
-def IIC_SSE_ALU_F32S_RM : InstrItinClass;
-def IIC_SSE_ALU_F64S_RR : InstrItinClass;
-def IIC_SSE_ALU_F64S_RM : InstrItinClass;
-def IIC_SSE_MUL_F32S_RR : InstrItinClass;
-def IIC_SSE_MUL_F32S_RM : InstrItinClass;
-def IIC_SSE_MUL_F64S_RR : InstrItinClass;
-def IIC_SSE_MUL_F64S_RM : InstrItinClass;
-def IIC_SSE_DIV_F32S_RR : InstrItinClass;
-def IIC_SSE_DIV_F32S_RM : InstrItinClass;
-def IIC_SSE_DIV_F64S_RR : InstrItinClass;
-def IIC_SSE_DIV_F64S_RM : InstrItinClass;
-def IIC_SSE_ALU_F32P_RR : InstrItinClass;
-def IIC_SSE_ALU_F32P_RM : InstrItinClass;
-def IIC_SSE_ALU_F64P_RR : InstrItinClass;
-def IIC_SSE_ALU_F64P_RM : InstrItinClass;
-def IIC_SSE_MUL_F32P_RR : InstrItinClass;
-def IIC_SSE_MUL_F32P_RM : InstrItinClass;
-def IIC_SSE_MUL_F64P_RR : InstrItinClass;
-def IIC_SSE_MUL_F64P_RM : InstrItinClass;
-def IIC_SSE_DIV_F32P_RR : InstrItinClass;
-def IIC_SSE_DIV_F32P_RM : InstrItinClass;
-def IIC_SSE_DIV_F64P_RR : InstrItinClass;
-def IIC_SSE_DIV_F64P_RM : InstrItinClass;
-
-def IIC_SSE_COMIS_RR : InstrItinClass;
-def IIC_SSE_COMIS_RM : InstrItinClass;
-
-def IIC_SSE_HADDSUB_RR : InstrItinClass;
-def IIC_SSE_HADDSUB_RM : InstrItinClass;
-
-def IIC_SSE_BIT_P_RR : InstrItinClass;
-def IIC_SSE_BIT_P_RM : InstrItinClass;
-
-def IIC_SSE_INTALU_P_RR : InstrItinClass;
-def IIC_SSE_INTALU_P_RM : InstrItinClass;
-def IIC_SSE_INTALUQ_P_RR : InstrItinClass;
-def IIC_SSE_INTALUQ_P_RM : InstrItinClass;
-
-def IIC_SSE_INTMUL_P_RR : InstrItinClass;
-def IIC_SSE_INTMUL_P_RM : InstrItinClass;
-
-def IIC_SSE_INTSH_P_RR : InstrItinClass;
-def IIC_SSE_INTSH_P_RM : InstrItinClass;
-def IIC_SSE_INTSH_P_RI : InstrItinClass;
-
-def IIC_SSE_INTSHDQ_P_RI : InstrItinClass;
-
-def IIC_SSE_SHUFP : InstrItinClass;
-def IIC_SSE_PSHUF_RI : InstrItinClass;
-def IIC_SSE_PSHUF_MI : InstrItinClass;
-
-def IIC_SSE_PACK : InstrItinClass;
-def IIC_SSE_UNPCK : InstrItinClass;
-
-def IIC_SSE_PABS_RR : InstrItinClass;
-def IIC_SSE_PABS_RM : InstrItinClass;
-
-def IIC_SSE_SQRTPS_RR : InstrItinClass;
-def IIC_SSE_SQRTPS_RM : InstrItinClass;
-def IIC_SSE_SQRTSS_RR : InstrItinClass;
-def IIC_SSE_SQRTSS_RM : InstrItinClass;
-def IIC_SSE_SQRTPD_RR : InstrItinClass;
-def IIC_SSE_SQRTPD_RM : InstrItinClass;
-def IIC_SSE_SQRTSD_RR : InstrItinClass;
-def IIC_SSE_SQRTSD_RM : InstrItinClass;
-
-def IIC_SSE_RSQRTPS_RR : InstrItinClass;
-def IIC_SSE_RSQRTPS_RM : InstrItinClass;
-def IIC_SSE_RSQRTSS_RR : InstrItinClass;
-def IIC_SSE_RSQRTSS_RM : InstrItinClass;
-
-def IIC_SSE_RCPP_RR : InstrItinClass;
-def IIC_SSE_RCPP_RM : InstrItinClass;
-def IIC_SSE_RCPS_RR : InstrItinClass;
-def IIC_SSE_RCPS_RM : InstrItinClass;
-
-def IIC_SSE_MOV_S_RR : InstrItinClass;
-def IIC_SSE_MOV_S_RM : InstrItinClass;
-def IIC_SSE_MOV_S_MR : InstrItinClass;
-
-def IIC_SSE_MOVA_P_RR : InstrItinClass;
-def IIC_SSE_MOVA_P_RM : InstrItinClass;
-def IIC_SSE_MOVA_P_MR : InstrItinClass;
-
-def IIC_SSE_MOVU_P_RR : InstrItinClass;
-def IIC_SSE_MOVU_P_RM : InstrItinClass;
-def IIC_SSE_MOVU_P_MR : InstrItinClass;
-
-def IIC_SSE_MOV_LH : InstrItinClass;
-
-def IIC_SSE_PHADDSUBD_RR : InstrItinClass;
-def IIC_SSE_PHADDSUBD_RM : InstrItinClass;
-def IIC_SSE_PHADDSUBSW_RR : InstrItinClass;
-def IIC_SSE_PHADDSUBSW_RM : InstrItinClass;
-def IIC_SSE_PHADDSUBW_RR : InstrItinClass;
-def IIC_SSE_PHADDSUBW_RM : InstrItinClass;
-def IIC_SSE_PSHUFB_RR : InstrItinClass;
-def IIC_SSE_PSHUFB_RM : InstrItinClass;
-def IIC_SSE_PSIGN_RR : InstrItinClass;
-def IIC_SSE_PSIGN_RM : InstrItinClass;
-
-def IIC_SSE_PMADD : InstrItinClass;
-def IIC_SSE_PMULHRSW : InstrItinClass;
-def IIC_SSE_PALIGNRR : InstrItinClass;
-def IIC_SSE_PALIGNRM : InstrItinClass;
-def IIC_SSE_CVT_PD_RR : InstrItinClass;
-def IIC_SSE_CVT_PD_RM : InstrItinClass;
-def IIC_SSE_CVT_PS_RR : InstrItinClass;
-def IIC_SSE_CVT_PS_RM : InstrItinClass;
-def IIC_SSE_CVT_Scalar_RR : InstrItinClass;
-def IIC_SSE_CVT_Scalar_RM : InstrItinClass;
-def IIC_SSE_CVT_SS2SI32_RM : InstrItinClass;
-def IIC_SSE_CVT_SS2SI32_RR : InstrItinClass;
-def IIC_SSE_CVT_SS2SI64_RM : InstrItinClass;
-def IIC_SSE_CVT_SS2SI64_RR : InstrItinClass;
-def IIC_SSE_CVT_SD2SI_RM : InstrItinClass;
-def IIC_SSE_CVT_SD2SI_RR : InstrItinClass;
-
-def IIC_SSE_DPPD_RR : InstrItinClass;
-def IIC_SSE_DPPD_RM : InstrItinClass;
-def IIC_SSE_DPPS_RR : InstrItinClass;
-def IIC_SSE_DPPS_RM : InstrItinClass;
-def IIC_SSE_EXTRACTPS_RR : InstrItinClass;
-def IIC_SSE_EXTRACTPS_RM : InstrItinClass;
-def IIC_SSE_INSERTPS_RR : InstrItinClass;
-def IIC_SSE_INSERTPS_RM : InstrItinClass;
-def IIC_SSE_MPSADBW_RR : InstrItinClass;
-def IIC_SSE_MPSADBW_RM : InstrItinClass;
-def IIC_SSE_PMULLD_RR : InstrItinClass;
-def IIC_SSE_PMULLD_RM : InstrItinClass;
-def IIC_SSE_ROUNDPS_REG : InstrItinClass;
-def IIC_SSE_ROUNDPS_MEM : InstrItinClass;
-def IIC_SSE_ROUNDPD_REG : InstrItinClass;
-def IIC_SSE_ROUNDPD_MEM : InstrItinClass;
-
-//===----------------------------------------------------------------------===//
// Generic Processor Scheduler Models.
// IssueWidth is analogous to the number of decode units. Core and its
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