[PATCH] D45204: [X86][MIPS][ARM] New machine instruction property 'isMoveReg'

[Nikola Prica via Phabricator via llvm-commits]

NikolaPrica added inline comments.


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Comment at: lib/Target/X86/X86InstrAVX512.td:2749
                              RegisterClass KRC, RegisterClass GRC> {
-  let hasSideEffects = 0 in {
+  let hasSideEffects = 0, isMoveReg = 1 in {
     def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
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craig.topper wrote:
> The widths of the registers don't always match here. Is that a problem? Bits are either truncated or zero extended.
If bits are truncated then it can be a problem. I will remove this then.


https://reviews.llvm.org/D45204