[llvm] r329905 - [mips] Correct the predicates for special nops, tlb ctrl instrs, software breakpoint and prefx.
Simon Dardis via llvm-commits
llvm-commits at lists.llvm.org
Thu Apr 12 05:37:03 PDT 2018
Author: sdardis
Date: Thu Apr 12 05:37:02 2018
New Revision: 329905
URL: http://llvm.org/viewvc/llvm-project?rev=329905&view=rev
Log:
[mips] Correct the predicates for special nops, tlb ctrl instrs, software breakpoint and prefx.
Reviewers: atanasyan, abeserminji
Differential Revision: https://reviews.llvm.org/D44436
Modified:
llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td
llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt
llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid.txt
llvm/trunk/test/MC/Disassembler/Mips/mips32r2/valid-mips32r2-el.txt
llvm/trunk/test/MC/Disassembler/Mips/mips32r2/valid-mips32r2.txt
llvm/trunk/test/MC/Disassembler/Mips/mips32r3/valid-mips32r3-el.txt
llvm/trunk/test/MC/Disassembler/Mips/mips32r3/valid-mips32r3.txt
llvm/trunk/test/MC/Disassembler/Mips/mips32r5/valid-mips32r5-el.txt
llvm/trunk/test/MC/Disassembler/Mips/mips32r5/valid-mips32r5.txt
llvm/trunk/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6-el.txt
llvm/trunk/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt
llvm/trunk/test/MC/Disassembler/Mips/mips64r2/valid-mips64r2-el.txt
llvm/trunk/test/MC/Disassembler/Mips/mips64r2/valid-mips64r2.txt
llvm/trunk/test/MC/Disassembler/Mips/mips64r3/valid-mips64r3-el.txt
llvm/trunk/test/MC/Disassembler/Mips/mips64r3/valid-mips64r3.txt
llvm/trunk/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5-el.txt
llvm/trunk/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5.txt
llvm/trunk/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt
llvm/trunk/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt
llvm/trunk/test/MC/Mips/mips1/valid.s
llvm/trunk/test/MC/Mips/mips2/valid.s
llvm/trunk/test/MC/Mips/mips3/valid.s
llvm/trunk/test/MC/Mips/mips32/valid.s
llvm/trunk/test/MC/Mips/mips32r2/valid.s
llvm/trunk/test/MC/Mips/mips32r3/valid.s
llvm/trunk/test/MC/Mips/mips32r5/valid.s
llvm/trunk/test/MC/Mips/mips32r6/valid.s
llvm/trunk/test/MC/Mips/mips4/valid.s
llvm/trunk/test/MC/Mips/mips5/valid.s
llvm/trunk/test/MC/Mips/mips64/valid.s
llvm/trunk/test/MC/Mips/mips64r2/valid.s
llvm/trunk/test/MC/Mips/mips64r3/valid.s
llvm/trunk/test/MC/Mips/mips64r5/valid.s
llvm/trunk/test/MC/Mips/mips64r6/valid.s
Modified: llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td?rev=329905&r1=329904&r2=329905&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td Thu Apr 12 05:37:02 2018
@@ -1006,20 +1006,27 @@ let DecoderNamespace = "MicroMips" in {
def CACHEE_MM : MMRel, CacheOp<"cachee", mem_mm_9, II_CACHEE>,
CACHE_PREFE_FM_MM<0x18, 0x3>, ISA_MICROMIPS, ASE_EVA;
}
-}
-let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
- def SSNOP_MM : MMRel, Barrier<"ssnop", II_SSNOP>, BARRIER_FM_MM<0x1>;
- def EHB_MM : MMRel, Barrier<"ehb", II_EHB>, BARRIER_FM_MM<0x3>;
- def PAUSE_MM : MMRel, Barrier<"pause", II_PAUSE>, BARRIER_FM_MM<0x5>;
+ def SSNOP_MM : MMRel, Barrier<"ssnop", II_SSNOP>, BARRIER_FM_MM<0x1>,
+ ISA_MICROMIPS;
+ def EHB_MM : MMRel, Barrier<"ehb", II_EHB>, BARRIER_FM_MM<0x3>,
+ ISA_MICROMIPS;
+ def PAUSE_MM : MMRel, Barrier<"pause", II_PAUSE>, BARRIER_FM_MM<0x5>,
+ ISA_MICROMIPS;
- def TLBP_MM : MMRel, TLB<"tlbp", II_TLBP>, COP0_TLB_FM_MM<0x0d>;
- def TLBR_MM : MMRel, TLB<"tlbr", II_TLBR>, COP0_TLB_FM_MM<0x4d>;
- def TLBWI_MM : MMRel, TLB<"tlbwi", II_TLBWI>, COP0_TLB_FM_MM<0x8d>;
- def TLBWR_MM : MMRel, TLB<"tlbwr", II_TLBWR>, COP0_TLB_FM_MM<0xcd>;
+ def TLBP_MM : MMRel, TLB<"tlbp", II_TLBP>, COP0_TLB_FM_MM<0x0d>,
+ ISA_MICROMIPS;
+ def TLBR_MM : MMRel, TLB<"tlbr", II_TLBR>, COP0_TLB_FM_MM<0x4d>,
+ ISA_MICROMIPS;
+ def TLBWI_MM : MMRel, TLB<"tlbwi", II_TLBWI>, COP0_TLB_FM_MM<0x8d>,
+ ISA_MICROMIPS;
+ def TLBWR_MM : MMRel, TLB<"tlbwr", II_TLBWR>, COP0_TLB_FM_MM<0xcd>,
+ ISA_MICROMIPS;
- def SDBBP_MM : MMRel, SYS_FT<"sdbbp", uimm10, II_SDBBP>, SDBBP_FM_MM;
+ def SDBBP_MM : MMRel, SYS_FT<"sdbbp", uimm10, II_SDBBP>, SDBBP_FM_MM,
+ ISA_MICROMIPS;
- def PREFX_MM : PrefetchIndexed<"prefx">, POOL32F_PREFX_FM_MM<0x15, 0x1A0>;
+ def PREFX_MM : PrefetchIndexed<"prefx">, POOL32F_PREFX_FM_MM<0x15, 0x1A0>,
+ ISA_MICROMIPS32_NOT_MIPS32R6;
}
def TAILCALL_MM : TailCall<J_MM, jmptarget_mm>, ISA_MIPS1_NOT_32R6_64R6;
Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=329905&r1=329904&r2=329905&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Thu Apr 12 05:37:02 2018
@@ -2324,13 +2324,15 @@ let AdditionalPredicates = [NotInMicroMi
class Barrier<string asmstr, InstrItinClass itin = NoItinerary> :
InstSE<(outs), (ins), asmstr, [], itin, FrmOther, asmstr>;
-
-def SSNOP : MMRel, StdMMR6Rel, Barrier<"ssnop", II_SSNOP>, BARRIER_FM<1>;
-def EHB : MMRel, Barrier<"ehb", II_EHB>, BARRIER_FM<3>;
-
-let isCTI = 1 in
-def PAUSE : MMRel, StdMMR6Rel, Barrier<"pause", II_PAUSE>, BARRIER_FM<5>,
- ISA_MIPS32R2;
+let AdditionalPredicates = [NotInMicroMips] in {
+ def SSNOP : MMRel, StdMMR6Rel, Barrier<"ssnop", II_SSNOP>, BARRIER_FM<1>,
+ ISA_MIPS1;
+ def EHB : MMRel, Barrier<"ehb", II_EHB>, BARRIER_FM<3>, ISA_MIPS1;
+
+ let isCTI = 1 in
+ def PAUSE : MMRel, StdMMR6Rel, Barrier<"pause", II_PAUSE>, BARRIER_FM<5>,
+ ISA_MIPS32R2;
+}
// JR_HB and JALR_HB are defined here using the new style naming
// scheme because some of this code is shared with Mips32r6InstrInfo.td
@@ -2389,10 +2391,10 @@ let AdditionalPredicates = [NotInMips16M
class TLB<string asmstr, InstrItinClass itin = NoItinerary> :
InstSE<(outs), (ins), asmstr, [], itin, FrmOther, asmstr>;
let AdditionalPredicates = [NotInMicroMips] in {
-def TLBP : MMRel, TLB<"tlbp", II_TLBP>, COP0_TLB_FM<0x08>;
-def TLBR : MMRel, TLB<"tlbr", II_TLBR>, COP0_TLB_FM<0x01>;
-def TLBWI : MMRel, TLB<"tlbwi", II_TLBWI>, COP0_TLB_FM<0x02>;
-def TLBWR : MMRel, TLB<"tlbwr", II_TLBWR>, COP0_TLB_FM<0x06>;
+ def TLBP : MMRel, TLB<"tlbp", II_TLBP>, COP0_TLB_FM<0x08>, ISA_MIPS1;
+ def TLBR : MMRel, TLB<"tlbr", II_TLBR>, COP0_TLB_FM<0x01>, ISA_MIPS1;
+ def TLBWI : MMRel, TLB<"tlbwi", II_TLBWI>, COP0_TLB_FM<0x02>, ISA_MIPS1;
+ def TLBWR : MMRel, TLB<"tlbwr", II_TLBWR>, COP0_TLB_FM<0x06>, ISA_MIPS1;
}
class CacheOp<string instr_asm, Operand MemOpnd,
InstrItinClass itin = NoItinerary> :
@@ -2406,7 +2408,7 @@ def CACHE : MMRel, CacheOp<"cache", mem,
INSN_MIPS3_32_NOT_32R6_64R6;
def PREF : MMRel, CacheOp<"pref", mem, II_PREF>, CACHEOP_FM<0b110011>,
INSN_MIPS3_32_NOT_32R6_64R6;
-
+// FIXME: We are missing the prefx instruction.
def ROL : MipsAsmPseudoInst<(outs),
(ins GPR32Opnd:$rs, GPR32Opnd:$rt, GPR32Opnd:$rd),
"rol\t$rs, $rt, $rd">;
Modified: llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt?rev=329905&r1=329904&r2=329905&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt Thu Apr 12 05:37:02 2018
@@ -138,6 +138,10 @@
0x86 0x40 0x9a 0x02 # CHECK: blez $6, 1336
0xc9 0xb4 0x9a 0x02 # CHECK: bne $9, $6, 1336
0x06 0x40 0x9a 0x02 # CHECK: bltz $6, 1336
+0x00 0x00 0x7c 0x03 # CHECK: tlbp
+0x00 0x00 0x7c 0x13 # CHECK: tlbr
+0x00 0x00 0x7c 0x23 # CHECK: tlbwi
+0x00 0x00 0x7c 0x33 # CHECK: tlbwr
0x28 0x01 0x3c 0x00 # CHECK: teq $8, $9
0x28 0x01 0x3c 0x02 # CHECK: tge $8, $9
0x28 0x01 0x3c 0x04 # CHECK: tgeu $8, $9
Modified: llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid.txt?rev=329905&r1=329904&r2=329905&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid.txt Thu Apr 12 05:37:02 2018
@@ -138,6 +138,10 @@
0x40 0x86 0x02 0x9a # CHECK: blez $6, 1336
0xb4 0xc9 0x02 0x9a # CHECK: bne $9, $6, 1336
0x40 0x06 0x02 0x9a # CHECK: bltz $6, 1336
+0x00 0x00 0x03 0x7c # CHECK: tlbp
+0x00 0x00 0x13 0x7c # CHECK: tlbr
+0x00 0x00 0x23 0x7c # CHECK: tlbwi
+0x00 0x00 0x33 0x7c # CHECK: tlbwr
0x01 0x28 0x00 0x3c # CHECK: teq $8, $9
0x01 0x28 0x02 0x3c # CHECK: tge $8, $9
0x01 0x28 0x04 0x3c # CHECK: tgeu $8, $9
Modified: llvm/trunk/test/MC/Disassembler/Mips/mips32r2/valid-mips32r2-el.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/mips32r2/valid-mips32r2-el.txt?rev=329905&r1=329904&r2=329905&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mips32r2/valid-mips32r2-el.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/mips32r2/valid-mips32r2-el.txt Thu Apr 12 05:37:02 2018
@@ -24,6 +24,7 @@
0x4c 0x01 0xc0 0x1c # CHECK: bgtz $6, 1332
0x4c 0x01 0xc0 0x18 # CHECK: blez $6, 1332
0x4c 0x01 0x26 0x15 # CHECK: bne $9, $6, 1332
+0x40 0x01 0x00 0x00 # CHECK: pause
0x32 0x60 0x2e 0x46 # CHECK: c.eq.d $f12, $f14
0x32 0x30 0x07 0x46 # CHECK: c.eq.s $f6, $f7
0x30 0x60 0x2e 0x46 # CHECK: c.f.d $f12, $f14
Modified: llvm/trunk/test/MC/Disassembler/Mips/mips32r2/valid-mips32r2.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/mips32r2/valid-mips32r2.txt?rev=329905&r1=329904&r2=329905&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mips32r2/valid-mips32r2.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/mips32r2/valid-mips32r2.txt Thu Apr 12 05:37:02 2018
@@ -12,6 +12,7 @@
0x00 0x00 0x00 0x40 # CHECK: ssnop
0x00 0x00 0x00 0x80 # CHECK: sll $zero, $zero, 2
0x00 0x00 0x00 0xc0 # CHECK: ehb
+0x00 0x00 0x01 0x40 # CHECK: pause
0x00 0x00 0x01 0xcf # CHECK: sync 7
0x00 0x00 0x28 0x09 # CHECK: jalr $5, $zero
0x00 0x00 0x28 0x10 # CHECK: mfhi $5
Modified: llvm/trunk/test/MC/Disassembler/Mips/mips32r3/valid-mips32r3-el.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/mips32r3/valid-mips32r3-el.txt?rev=329905&r1=329904&r2=329905&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mips32r3/valid-mips32r3-el.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/mips32r3/valid-mips32r3-el.txt Thu Apr 12 05:37:02 2018
@@ -21,6 +21,7 @@
0x4c 0x01 0xc0 0x1c # CHECK: bgtz $6, 1332
0x4c 0x01 0xc0 0x18 # CHECK: blez $6, 1332
0x4c 0x01 0x26 0x15 # CHECK: bne $9, $6, 1332
+0x40 0x01 0x00 0x00 # CHECK: pause
0x32 0x60 0x2e 0x46 # CHECK: c.eq.d $f12, $f14
0x32 0x30 0x07 0x46 # CHECK: c.eq.s $f6, $f7
0x30 0x60 0x2e 0x46 # CHECK: c.f.d $f12, $f14
Modified: llvm/trunk/test/MC/Disassembler/Mips/mips32r3/valid-mips32r3.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/mips32r3/valid-mips32r3.txt?rev=329905&r1=329904&r2=329905&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mips32r3/valid-mips32r3.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/mips32r3/valid-mips32r3.txt Thu Apr 12 05:37:02 2018
@@ -9,6 +9,7 @@
0x00 0x00 0x00 0x40 # CHECK: ssnop
0x00 0x00 0x00 0x80 # CHECK: sll $zero, $zero, 2
0x00 0x00 0x00 0xc0 # CHECK: ehb
+0x00 0x00 0x01 0x40 # CHECK: pause
0x00 0x00 0x01 0xcf # CHECK: sync 7
0x00 0x00 0x28 0x09 # CHECK: jalr $5, $zero
0x00 0x00 0x28 0x10 # CHECK: mfhi $5
Modified: llvm/trunk/test/MC/Disassembler/Mips/mips32r5/valid-mips32r5-el.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/mips32r5/valid-mips32r5-el.txt?rev=329905&r1=329904&r2=329905&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mips32r5/valid-mips32r5-el.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/mips32r5/valid-mips32r5-el.txt Thu Apr 12 05:37:02 2018
@@ -21,6 +21,7 @@
0x4c 0x01 0xc0 0x1c # CHECK: bgtz $6, 1332
0x4c 0x01 0xc0 0x18 # CHECK: blez $6, 1332
0x4c 0x01 0x26 0x15 # CHECK: bne $9, $6, 1332
+0x40 0x01 0x00 0x00 # CHECK: pause
0x32 0x60 0x2e 0x46 # CHECK: c.eq.d $f12, $f14
0x32 0x30 0x07 0x46 # CHECK: c.eq.s $f6, $f7
0x30 0x60 0x2e 0x46 # CHECK: c.f.d $f12, $f14
Modified: llvm/trunk/test/MC/Disassembler/Mips/mips32r5/valid-mips32r5.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/mips32r5/valid-mips32r5.txt?rev=329905&r1=329904&r2=329905&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mips32r5/valid-mips32r5.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/mips32r5/valid-mips32r5.txt Thu Apr 12 05:37:02 2018
@@ -9,6 +9,7 @@
0x00 0x00 0x00 0x40 # CHECK: ssnop
0x00 0x00 0x00 0x80 # CHECK: sll $zero, $zero, 2
0x00 0x00 0x00 0xc0 # CHECK: ehb
+0x00 0x00 0x01 0x40 # CHECK: pause
0x00 0x00 0x01 0xcf # CHECK: sync 7
0x00 0x00 0x28 0x09 # CHECK: jalr $5, $zero
0x00 0x00 0x28 0x10 # CHECK: mfhi $5
Modified: llvm/trunk/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6-el.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6-el.txt?rev=329905&r1=329904&r2=329905&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6-el.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6-el.txt Thu Apr 12 05:37:02 2018
@@ -17,6 +17,7 @@
0x02 0x00 0x3f 0x49 # CHECK: bc2eqz $31, 12
0x02 0x00 0xa0 0x49 # CHECK: bc2nez $0, 12
0x02 0x00 0xbf 0x49 # CHECK: bc2nez $31, 12
+0x40 0x01 0x00 0x00 # CHECK: pause
0x40 0x00 0xa6 0x20 # CHECK: beqc $5, $6, 260
0x4d 0x01 0x02 0x20 # CHECK: beqzalc $2, 1336
0x40 0x00 0xa6 0x60 # CHECK: bnec $5, $6, 260
Modified: llvm/trunk/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt?rev=329905&r1=329904&r2=329905&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt Thu Apr 12 05:37:02 2018
@@ -3,6 +3,8 @@
0x00 0x00 0x00 0x0f # CHECK: sync
0x00 0x00 0x00 0x40 # CHECK: ssnop
0x00 0x00 0x00 0x4f # CHECK: sync 1
+0x00 0x00 0x00 0xc0 # CHECK: ehb
+0x00 0x00 0x01 0x40 # CHECK: pause
0x00 0x00 0x08 0x8e # CHECK: sdbbp 34
0x00 0x03 0x00 0x34 # CHECK: teq $zero, $3
0x00 0x53 0x21 0x72 # CHECK: tlt $2, $19, 133
Modified: llvm/trunk/test/MC/Disassembler/Mips/mips64r2/valid-mips64r2-el.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/mips64r2/valid-mips64r2-el.txt?rev=329905&r1=329904&r2=329905&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mips64r2/valid-mips64r2-el.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/mips64r2/valid-mips64r2-el.txt Thu Apr 12 05:37:02 2018
@@ -24,6 +24,7 @@
0x4c 0x01 0xc0 0x1c # CHECK: bgtz $6, 1332
0x4c 0x01 0xc0 0x18 # CHECK: blez $6, 1332
0x4c 0x01 0x26 0x15 # CHECK: bne $9, $6, 1332
+0x40 0x01 0x00 0x00 # CHECK: pause
0x32 0x60 0x2e 0x46 # CHECK: c.eq.d $f12, $f14
0x32 0x30 0x07 0x46 # CHECK: c.eq.s $f6, $f7
0x30 0x60 0x2e 0x46 # CHECK: c.f.d $f12, $f14
Modified: llvm/trunk/test/MC/Disassembler/Mips/mips64r2/valid-mips64r2.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/mips64r2/valid-mips64r2.txt?rev=329905&r1=329904&r2=329905&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mips64r2/valid-mips64r2.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/mips64r2/valid-mips64r2.txt Thu Apr 12 05:37:02 2018
@@ -12,6 +12,7 @@
0x00 0x00 0x00 0x40 # CHECK: ssnop
0x00 0x00 0x00 0x80 # CHECK: sll $zero, $zero, 2
0x00 0x00 0x00 0xc0 # CHECK: ehb
+0x00 0x00 0x01 0x40 # CHECK: pause
0x00 0x00 0x01 0xcf # CHECK: sync 7
0x00 0x00 0x04 0xb8 # CHECK: dsll $zero, $zero, 18
0x00 0x00 0x04 0xbc # CHECK: dsll32 $zero, $zero, 18
Modified: llvm/trunk/test/MC/Disassembler/Mips/mips64r3/valid-mips64r3-el.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/mips64r3/valid-mips64r3-el.txt?rev=329905&r1=329904&r2=329905&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mips64r3/valid-mips64r3-el.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/mips64r3/valid-mips64r3-el.txt Thu Apr 12 05:37:02 2018
@@ -21,6 +21,7 @@
0x4c 0x01 0xc0 0x1c # CHECK: bgtz $6, 1332
0x4c 0x01 0xc0 0x18 # CHECK: blez $6, 1332
0x4c 0x01 0x26 0x15 # CHECK: bne $9, $6, 1332
+0x40 0x01 0x00 0x00 # CHECK: pause
0x32 0x60 0x2e 0x46 # CHECK: c.eq.d $f12, $f14
0x32 0x30 0x07 0x46 # CHECK: c.eq.s $f6, $f7
0x30 0x60 0x2e 0x46 # CHECK: c.f.d $f12, $f14
Modified: llvm/trunk/test/MC/Disassembler/Mips/mips64r3/valid-mips64r3.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/mips64r3/valid-mips64r3.txt?rev=329905&r1=329904&r2=329905&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mips64r3/valid-mips64r3.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/mips64r3/valid-mips64r3.txt Thu Apr 12 05:37:02 2018
@@ -9,6 +9,7 @@
0x00 0x00 0x00 0x40 # CHECK: ssnop
0x00 0x00 0x00 0x80 # CHECK: sll $zero, $zero, 2
0x00 0x00 0x00 0xc0 # CHECK: ehb
+0x00 0x00 0x01 0x40 # CHECK: pause
0x00 0x00 0x01 0xcf # CHECK: sync 7
0x00 0x00 0x04 0xb8 # CHECK: dsll $zero, $zero, 18
0x00 0x00 0x04 0xbc # CHECK: dsll32 $zero, $zero, 18
Modified: llvm/trunk/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5-el.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5-el.txt?rev=329905&r1=329904&r2=329905&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5-el.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5-el.txt Thu Apr 12 05:37:02 2018
@@ -21,6 +21,7 @@
0x4c 0x01 0xc0 0x1c # CHECK: bgtz $6, 1332
0x4c 0x01 0xc0 0x18 # CHECK: blez $6, 1332
0x4c 0x01 0x26 0x15 # CHECK: bne $9, $6, 1332
+0x40 0x01 0x00 0x00 # CHECK: pause
0x32 0x60 0x2e 0x46 # CHECK: c.eq.d $f12, $f14
0x32 0x30 0x07 0x46 # CHECK: c.eq.s $f6, $f7
0x30 0x60 0x2e 0x46 # CHECK: c.f.d $f12, $f14
Modified: llvm/trunk/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5.txt?rev=329905&r1=329904&r2=329905&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5.txt Thu Apr 12 05:37:02 2018
@@ -9,6 +9,7 @@
0x00 0x00 0x00 0x40 # CHECK: ssnop
0x00 0x00 0x00 0x80 # CHECK: sll $zero, $zero, 2
0x00 0x00 0x00 0xc0 # CHECK: ehb
+0x00 0x00 0x01 0x40 # CHECK: pause
0x00 0x00 0x01 0xcf # CHECK: sync 7
0x00 0x00 0x04 0xb8 # CHECK: dsll $zero, $zero, 18
0x00 0x00 0x04 0xbc # CHECK: dsll32 $zero, $zero, 18
Modified: llvm/trunk/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt?rev=329905&r1=329904&r2=329905&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt Thu Apr 12 05:37:02 2018
@@ -17,6 +17,7 @@
0x02 0x00 0xa0 0x49 # CHECK: bc2nez $0, 12
0x02 0x00 0xbf 0x49 # CHECK: bc2nez $31, 12
0x40 0x00 0xa6 0x20 # CHECK: beqc $5, $6, 260
+0x40 0x01 0x00 0x00 # CHECK: pause
0x4d 0x01 0x02 0x20 # CHECK: beqzalc $2, 1336
0x90 0x46 0xa0 0xd8 # CHECK: beqzc $5, 72260
0xfa 0xff 0x5f 0xd8 # CHECK: beqzc $2, -20
Modified: llvm/trunk/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt?rev=329905&r1=329904&r2=329905&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt Thu Apr 12 05:37:02 2018
@@ -3,6 +3,8 @@
0x00 0x00 0x00 0x0f # CHECK: sync
0x00 0x00 0x00 0x40 # CHECK: ssnop
0x00 0x00 0x00 0x4f # CHECK: sync 1
+0x00 0x00 0x00 0xc0 # CHECK: ehb
+0x00 0x00 0x01 0x40 # CHECK: pause
0x00 0x00 0x08 0x8e # CHECK: sdbbp 34
0x00 0x03 0x00 0x34 # CHECK: teq $zero, $3
0x00 0x03 0x10 0x2e # CHECK: dneg $2, $3
Modified: llvm/trunk/test/MC/Mips/mips1/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips1/valid.s?rev=329905&r1=329904&r2=329905&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips1/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips1/valid.s Thu Apr 12 05:37:02 2018
@@ -49,6 +49,8 @@ a:
div.s $f4,$f5,$f15
divu $zero,$25,$15
ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} EHB
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} EHB_MM
j 1f # CHECK: j $tmp0 # encoding: [0b000010AA,A,A,A]
# CHECK: # fixup A - offset: 0, value: ($tmp0), kind: fixup_Mips_26
j a # CHECK: j a # encoding: [0b000010AA,A,A,A]
@@ -127,6 +129,8 @@ a:
srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SSNOP
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SSNOP_MM
sub $s6,$s3,$12
sub $22,$17,-3126 # CHECK: addi $22, $17, 3126 # encoding: [0x22,0x36,0x0c,0x36]
sub $13,6512 # CHECK: addi $13, $13, -6512 # encoding: [0x21,0xad,0xe6,0x90]
@@ -143,9 +147,17 @@ a:
syscall # CHECK: syscall # encoding: [0x00,0x00,0x00,0x0c]
syscall 256 # CHECK: syscall 256 # encoding: [0x00,0x00,0x40,0x0c]
tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} TLBP
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} TLBP_MM
tlbr # CHECK: tlbr # encoding: [0x42,0x00,0x00,0x01]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} TLBR
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} TLBR_MM
tlbwi # CHECK: tlbwi # encoding: [0x42,0x00,0x00,0x02]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} TLBWI
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} TLBWI_MM
tlbwr # CHECK: tlbwr # encoding: [0x42,0x00,0x00,0x06]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} TLBWR
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} TLBWR_MM
xor $s2,$a0,$s8
xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04]
Modified: llvm/trunk/test/MC/Mips/mips2/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips2/valid.s?rev=329905&r1=329904&r2=329905&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips2/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips2/valid.s Thu Apr 12 05:37:02 2018
@@ -188,9 +188,17 @@ a:
tgeu $22,$28 # CHECK: tgeu $22, $gp # encoding: [0x02,0xdc,0x00,0x31]
tgeu $20,$14,379 # CHECK: tgeu $20, $14, 379 # encoding: [0x02,0x8e,0x5e,0xf1]
tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} TLBP
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} TLBP_MM
tlbr # CHECK: tlbr # encoding: [0x42,0x00,0x00,0x01]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} TLBR
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} TLBR_MM
tlbwi # CHECK: tlbwi # encoding: [0x42,0x00,0x00,0x02]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} TLBWI
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} TLBWI_MM
tlbwr # CHECK: tlbwr # encoding: [0x42,0x00,0x00,0x06]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} TLBWR
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} TLBWR_MM
tlt $15,$13 # CHECK: tlt $15, $13 # encoding: [0x01,0xed,0x00,0x32]
tlt $2,$19,133 # CHECK: tlt $2, $19, 133 # encoding: [0x00,0x53,0x21,0x72]
tlti $14,-21059
Modified: llvm/trunk/test/MC/Mips/mips3/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips3/valid.s?rev=329905&r1=329904&r2=329905&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips3/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips3/valid.s Thu Apr 12 05:37:02 2018
@@ -1,6 +1,6 @@
# Instructions that are valid
#
-# RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips3 | FileCheck %s
+# RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -show-inst -mcpu=mips3 | FileCheck %s
a:
.set noat
abs.d $f7,$f25 # CHECK: encoding:
@@ -242,9 +242,17 @@ a:
tgeu $22,$28 # CHECK: tgeu $22, $gp # encoding: [0x02,0xdc,0x00,0x31]
tgeu $20,$14,379 # CHECK: tgeu $20, $14, 379 # encoding: [0x02,0x8e,0x5e,0xf1]
tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} TLBP
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} TLBP_MM
tlbr # CHECK: tlbr # encoding: [0x42,0x00,0x00,0x01]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} TLBR
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} TLBR_MM
tlbwi # CHECK: tlbwi # encoding: [0x42,0x00,0x00,0x02]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} TLBWI
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} TLBWI_MM
tlbwr # CHECK: tlbwr # encoding: [0x42,0x00,0x00,0x06]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} TLBWR
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} TLBWR_MM
tlt $15,$13 # CHECK: tlt $15, $13 # encoding: [0x01,0xed,0x00,0x32]
tlt $2,$19,133 # CHECK: tlt $2, $19, 133 # encoding: [0x00,0x53,0x21,0x72]
tlti $14,-21059
Modified: llvm/trunk/test/MC/Mips/mips32/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips32/valid.s?rev=329905&r1=329904&r2=329905&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips32/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips32/valid.s Thu Apr 12 05:37:02 2018
@@ -186,7 +186,11 @@ a:
sb $s6,-19857($14)
sc $15,18904($s3) # CHECK: sc $15, 18904($19) # encoding: [0xe2,0x6f,0x49,0xd8]
sdbbp # CHECK: sdbbp # encoding: [0x70,0x00,0x00,0x3f]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SDBBP
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SDBBP_MM
sdbbp 34 # CHECK: sdbbp 34 # encoding: [0x70,0x00,0x08,0xbf]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SDBBP
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SDBBP_MM
sdc1 $f31,30574($13)
sdc2 $20,23157($s2) # CHECK: sdc2 $20, 23157($18) # encoding: [0xfa,0x54,0x5a,0x75]
sgt $4, $5 # CHECK: slt $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2a]
@@ -245,9 +249,17 @@ a:
tgeu $22,$28 # CHECK: tgeu $22, $gp # encoding: [0x02,0xdc,0x00,0x31]
tgeu $20,$14,379 # CHECK: tgeu $20, $14, 379 # encoding: [0x02,0x8e,0x5e,0xf1]
tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} TLBP
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} TLBP_MM
tlbr # CHECK: tlbr # encoding: [0x42,0x00,0x00,0x01]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} TLBR
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} TLBR_MM
tlbwi # CHECK: tlbwi # encoding: [0x42,0x00,0x00,0x02]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} TLBWI
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} TLBWI_MM
tlbwr # CHECK: tlbwr # encoding: [0x42,0x00,0x00,0x06]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} TLBWR
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} TLBWR_MM
tlt $15,$13 # CHECK: tlt $15, $13 # encoding: [0x01,0xed,0x00,0x32]
tlt $2,$19,133 # CHECK: tlt $2, $19, 133 # encoding: [0x00,0x53,0x21,0x72]
tlti $14,-21059
Modified: llvm/trunk/test/MC/Mips/mips32r2/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips32r2/valid.s?rev=329905&r1=329904&r2=329905&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips32r2/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips32r2/valid.s Thu Apr 12 05:37:02 2018
@@ -203,6 +203,8 @@ a:
or $12,$s0,$sp
or $2, 4 # CHECK: ori $2, $2, 4 # encoding: [0x34,0x42,0x00,0x04]
pause # CHECK: pause # encoding: [0x00,0x00,0x01,0x40]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} PAUSE
+ # CHECK-NOT # <MCInst #{{[0-9}+}} PAUSE_MM
pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0xcc,0xa1,0x00,0x08]
# FIXME: Use the code generator in order to print the .set directives
# instead of the instruction printer.
@@ -224,7 +226,11 @@ a:
sb $s6,-19857($14)
sc $15,18904($s3) # CHECK: sc $15, 18904($19) # encoding: [0xe2,0x6f,0x49,0xd8]
sdbbp # CHECK: sdbbp # encoding: [0x70,0x00,0x00,0x3f]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SDBBP
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SDBBP_MM
sdbbp 34 # CHECK: sdbbp 34 # encoding: [0x70,0x00,0x08,0xbf]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SDBBP
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SDBBP_MM
sdc1 $f31,30574($13)
sdc2 $20,23157($s2) # CHECK: sdc2 $20, 23157($18) # encoding: [0xfa,0x54,0x5a,0x75]
sdxc1 $f11,$10($14)
@@ -290,9 +296,17 @@ a:
tgeu $22,$28 # CHECK: tgeu $22, $gp # encoding: [0x02,0xdc,0x00,0x31]
tgeu $20,$14,379 # CHECK: tgeu $20, $14, 379 # encoding: [0x02,0x8e,0x5e,0xf1]
tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} TLBP
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} TLBP_MM
tlbr # CHECK: tlbr # encoding: [0x42,0x00,0x00,0x01]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} TLBR
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} TLBR_MM
tlbwi # CHECK: tlbwi # encoding: [0x42,0x00,0x00,0x02]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} TLBWI
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} TLBWI_MM
tlbwr # CHECK: tlbwr # encoding: [0x42,0x00,0x00,0x06]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} TLBWR
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} TLBWR_MM
tlt $15,$13 # CHECK: tlt $15, $13 # encoding: [0x01,0xed,0x00,0x32]
tlt $2,$19,133 # CHECK: tlt $2, $19, 133 # encoding: [0x00,0x53,0x21,0x72]
tlti $14,-21059
Modified: llvm/trunk/test/MC/Mips/mips32r3/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips32r3/valid.s?rev=329905&r1=329904&r2=329905&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips32r3/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips32r3/valid.s Thu Apr 12 05:37:02 2018
@@ -203,6 +203,8 @@ a:
or $12,$s0,$sp
or $2, 4 # CHECK: ori $2, $2, 4 # encoding: [0x34,0x42,0x00,0x04]
pause # CHECK: pause # encoding: [0x00,0x00,0x01,0x40]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} PAUSE
+ # CHECK-NOT # <MCInst #{{[0-9}+}} PAUSE_MM
pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0xcc,0xa1,0x00,0x08]
# FIXME: Use the code generator in order to print the .set directives
# instead of the instruction printer.
@@ -224,7 +226,11 @@ a:
sb $s6,-19857($14)
sc $15,18904($s3) # CHECK: sc $15, 18904($19) # encoding: [0xe2,0x6f,0x49,0xd8]
sdbbp # CHECK: sdbbp # encoding: [0x70,0x00,0x00,0x3f]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SDBBP
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SDBBP_MM
sdbbp 34 # CHECK: sdbbp 34 # encoding: [0x70,0x00,0x08,0xbf]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SDBBP
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SDBBP_MM
sdc1 $f31,30574($13)
sdc2 $20,23157($s2) # CHECK: sdc2 $20, 23157($18) # encoding: [0xfa,0x54,0x5a,0x75]
sdxc1 $f11,$10($14)
@@ -290,9 +296,17 @@ a:
tgeu $22,$28 # CHECK: tgeu $22, $gp # encoding: [0x02,0xdc,0x00,0x31]
tgeu $20,$14,379 # CHECK: tgeu $20, $14, 379 # encoding: [0x02,0x8e,0x5e,0xf1]
tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} TLBP
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} TLBP_MM
tlbr # CHECK: tlbr # encoding: [0x42,0x00,0x00,0x01]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} TLBR
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} TLBR_MM
tlbwi # CHECK: tlbwi # encoding: [0x42,0x00,0x00,0x02]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} TLBWI
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} TLBWI_MM
tlbwr # CHECK: tlbwr # encoding: [0x42,0x00,0x00,0x06]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} TLBWR
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} TLBWR_MM
tlt $15,$13 # CHECK: tlt $15, $13 # encoding: [0x01,0xed,0x00,0x32]
tlt $2,$19,133 # CHECK: tlt $2, $19, 133 # encoding: [0x00,0x53,0x21,0x72]
tlti $14,-21059
Modified: llvm/trunk/test/MC/Mips/mips32r5/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips32r5/valid.s?rev=329905&r1=329904&r2=329905&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips32r5/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips32r5/valid.s Thu Apr 12 05:37:02 2018
@@ -204,6 +204,8 @@ a:
or $12,$s0,$sp
or $2, 4 # CHECK: ori $2, $2, 4 # encoding: [0x34,0x42,0x00,0x04]
pause # CHECK: pause # encoding: [0x00,0x00,0x01,0x40]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} PAUSE
+ # CHECK-NOT # <MCInst #{{[0-9}+}} PAUSE_MM
pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0xcc,0xa1,0x00,0x08]
# FIXME: Use the code generator in order to print the .set directives
# instead of the instruction printer.
@@ -225,7 +227,11 @@ a:
sb $s6,-19857($14)
sc $15,18904($s3) # CHECK: sc $15, 18904($19) # encoding: [0xe2,0x6f,0x49,0xd8]
sdbbp # CHECK: sdbbp # encoding: [0x70,0x00,0x00,0x3f]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SDBBP
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SDBBP_MM
sdbbp 34 # CHECK: sdbbp 34 # encoding: [0x70,0x00,0x08,0xbf]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SDBBP
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SDBBP_MM
sdc1 $f31,30574($13)
sdc2 $20,23157($s2) # CHECK: sdc2 $20, 23157($18) # encoding: [0xfa,0x54,0x5a,0x75]
sdxc1 $f11,$10($14)
@@ -291,9 +297,17 @@ a:
tgeu $22,$28 # CHECK: tgeu $22, $gp # encoding: [0x02,0xdc,0x00,0x31]
tgeu $20,$14,379 # CHECK: tgeu $20, $14, 379 # encoding: [0x02,0x8e,0x5e,0xf1]
tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} TLBP
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} TLBP_MM
tlbr # CHECK: tlbr # encoding: [0x42,0x00,0x00,0x01]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} TLBR
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} TLBR_MM
tlbwi # CHECK: tlbwi # encoding: [0x42,0x00,0x00,0x02]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} TLBWI
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} TLBWI_MM
tlbwr # CHECK: tlbwr # encoding: [0x42,0x00,0x00,0x06]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} TLBWR
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} TLBWR_MM
tlt $15,$13 # CHECK: tlt $15, $13 # encoding: [0x01,0xed,0x00,0x32]
tlt $2,$19,133 # CHECK: tlt $2, $19, 133 # encoding: [0x00,0x53,0x21,0x72]
tlti $14,-21059
Modified: llvm/trunk/test/MC/Mips/mips32r6/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips32r6/valid.s?rev=329905&r1=329904&r2=329905&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips32r6/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips32r6/valid.s Thu Apr 12 05:37:02 2018
@@ -140,6 +140,9 @@ a:
negu $2,$3 # CHECK: negu $2, $3 # encoding: [0x00,0x03,0x10,0x23]
not $3, $4 # CHECK: not $3, $4 # encoding: [0x00,0x80,0x18,0x27]
not $3 # CHECK: not $3, $3 # encoding: [0x00,0x60,0x18,0x27]
+ pause # CHECK: pause # encoding: [0x00,0x00,0x01,0x40]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} PAUSE
+ # CHECK-NOT # <MCInst #{{[0-9}+}} PAUSE_MM
pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0x7c,0xa1,0x04,0x35]
# FIXME: Use the code generator in order to print the .set directives
# instead of the instruction printer.
@@ -211,11 +214,27 @@ a:
ssnop # WARNING: [[@LINE]]:9: warning: ssnop is deprecated for MIPS32r6 and is equivalent to a nop instruction
ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40]
sdbbp # CHECK: sdbbp # encoding: [0x00,0x00,0x00,0x0e]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SDBBP
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SDBBP_MM
sdbbp 34 # CHECK: sdbbp 34 # encoding: [0x00,0x00,0x08,0x8e]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SDBBP
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SDBBP_MM
sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f]
sync 1 # CHECK: sync 1 # encoding: [0x00,0x00,0x00,0x4f]
syscall # CHECK: syscall # encoding: [0x00,0x00,0x00,0x0c]
syscall 256 # CHECK: syscall 256 # encoding: [0x00,0x00,0x40,0x0c]
+ tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} TLBP
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} TLBP_MM
+ tlbr # CHECK: tlbr # encoding: [0x42,0x00,0x00,0x01]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} TLBR
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} TLBR_MM
+ tlbwi # CHECK: tlbwi # encoding: [0x42,0x00,0x00,0x02]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} TLBWI
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} TLBWI_MM
+ tlbwr # CHECK: tlbwr # encoding: [0x42,0x00,0x00,0x06]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} TLBWR
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} TLBWR_MM
teq $0,$3 # CHECK: teq $zero, $3 # encoding: [0x00,0x03,0x00,0x34]
teq $5,$7,620 # CHECK: teq $5, $7, 620 # encoding: [0x00,0xa7,0x9b,0x34]
tge $7,$10 # CHECK: tge $7, $10 # encoding: [0x00,0xea,0x00,0x30]
Modified: llvm/trunk/test/MC/Mips/mips4/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips4/valid.s?rev=329905&r1=329904&r2=329905&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips4/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips4/valid.s Thu Apr 12 05:37:02 2018
@@ -1,6 +1,6 @@
# Instructions that are valid
#
-# RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips4 | FileCheck %s
+# RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -show-inst -mcpu=mips4 | FileCheck %s
a:
.set noat
abs.d $f7,$f25 # CHECK: encoding:
@@ -303,9 +303,17 @@ a:
tgeu $22,$28 # CHECK: tgeu $22, $gp # encoding: [0x02,0xdc,0x00,0x31]
tgeu $20,$14,379 # CHECK: tgeu $20, $14, 379 # encoding: [0x02,0x8e,0x5e,0xf1]
tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} TLBP
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} TLBP_MM
tlbr # CHECK: tlbr # encoding: [0x42,0x00,0x00,0x01]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} TLBR
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} TLBR_MM
tlbwi # CHECK: tlbwi # encoding: [0x42,0x00,0x00,0x02]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} TLBWI
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} TLBWI_MM
tlbwr # CHECK: tlbwr # encoding: [0x42,0x00,0x00,0x06]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} TLBWR
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} TLBWR_MM
tlt $15,$13 # CHECK: tlt $15, $13 # encoding: [0x01,0xed,0x00,0x32]
tlt $2,$19,133 # CHECK: tlt $2, $19, 133 # encoding: [0x00,0x53,0x21,0x72]
tlti $14,-21059
Modified: llvm/trunk/test/MC/Mips/mips5/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips5/valid.s?rev=329905&r1=329904&r2=329905&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips5/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips5/valid.s Thu Apr 12 05:37:02 2018
@@ -1,6 +1,6 @@
# Instructions that are valid
#
-# RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips5 | FileCheck %s
+# RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -show-inst -mcpu=mips5 | FileCheck %s
a:
.set noat
abs.d $f7,$f25 # CHECK: encoding:
@@ -305,9 +305,17 @@ a:
tgeu $22,$28 # CHECK: tgeu $22, $gp # encoding: [0x02,0xdc,0x00,0x31]
tgeu $20,$14,379 # CHECK: tgeu $20, $14, 379 # encoding: [0x02,0x8e,0x5e,0xf1]
tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} TLBP
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} TLBP_MM
tlbr # CHECK: tlbr # encoding: [0x42,0x00,0x00,0x01]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} TLBR
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} TLBR_MM
tlbwi # CHECK: tlbwi # encoding: [0x42,0x00,0x00,0x02]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} TLBWI
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} TLBWI_MM
tlbwr # CHECK: tlbwr # encoding: [0x42,0x00,0x00,0x06]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} TLBWR
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} TLBWR_MM
tlt $15,$13 # CHECK: tlt $15, $13 # encoding: [0x01,0xed,0x00,0x32]
tlt $2,$19,133 # CHECK: tlt $2, $19, 133 # encoding: [0x00,0x53,0x21,0x72]
tlti $14,-21059
Modified: llvm/trunk/test/MC/Mips/mips64/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64/valid.s?rev=329905&r1=329904&r2=329905&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips64/valid.s Thu Apr 12 05:37:02 2018
@@ -1,6 +1,6 @@
# Instructions that are valid
#
-# RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64 | FileCheck %s
+# RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -show-inst -mcpu=mips64 | FileCheck %s
a:
.set noat
abs.d $f7,$f25 # CHECK: encoding:
@@ -323,9 +323,17 @@ a:
tgeu $22,$28 # CHECK: tgeu $22, $gp # encoding: [0x02,0xdc,0x00,0x31]
tgeu $20,$14,379 # CHECK: tgeu $20, $14, 379 # encoding: [0x02,0x8e,0x5e,0xf1]
tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} TLBP
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} TLBP_MM
tlbr # CHECK: tlbr # encoding: [0x42,0x00,0x00,0x01]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} TLBR
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} TLBR_MM
tlbwi # CHECK: tlbwi # encoding: [0x42,0x00,0x00,0x02]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} TLBWI
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} TLBWI_MM
tlbwr # CHECK: tlbwr # encoding: [0x42,0x00,0x00,0x06]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} TLBWR
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} TLBWR_MM
tlt $15,$13 # CHECK: tlt $15, $13 # encoding: [0x01,0xed,0x00,0x32]
tlt $2,$19,133 # CHECK: tlt $2, $19, 133 # encoding: [0x00,0x53,0x21,0x72]
tlti $14,-21059
Modified: llvm/trunk/test/MC/Mips/mips64r2/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64r2/valid.s?rev=329905&r1=329904&r2=329905&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64r2/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips64r2/valid.s Thu Apr 12 05:37:02 2018
@@ -1,6 +1,6 @@
# Instructions that are valid
#
-# RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64r2 | FileCheck %s
+# RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -show-inst -mcpu=mips64r2 | FileCheck %s
a:
.set noat
abs.d $f7,$f25 # CHECK: encoding:
@@ -267,6 +267,8 @@ a:
or $12,$s0,$sp
or $2, 4 # CHECK: ori $2, $2, 4 # encoding: [0x34,0x42,0x00,0x04]
pause # CHECK: pause # encoding: [0x00,0x00,0x01,0x40]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} PAUSE
+ # CHECK-NOT # <MCInst #{{[0-9}+}} PAUSE_MM
pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0xcc,0xa1,0x00,0x08]
# FIXME: Use the code generator in order to print the .set directives
# instead of the instruction printer.
@@ -291,7 +293,11 @@ a:
sc $15,18904($s3) # CHECK: sc $15, 18904($19) # encoding: [0xe2,0x6f,0x49,0xd8]
scd $15,-8243($sp) # CHECK: scd $15, -8243($sp) # encoding: [0xf3,0xaf,0xdf,0xcd]
sdbbp # CHECK: sdbbp # encoding: [0x70,0x00,0x00,0x3f]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SDBBP
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SDBBP_MM
sdbbp 34 # CHECK: sdbbp 34 # encoding: [0x70,0x00,0x08,0xbf]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SDBBP
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SDBBP_MM
sd $12,5835($10)
sdc1 $f31,30574($13)
sdc2 $20,23157($s2) # CHECK: sdc2 $20, 23157($18) # encoding: [0xfa,0x54,0x5a,0x75]
@@ -357,9 +363,17 @@ a:
tgeu $22,$28 # CHECK: tgeu $22, $gp # encoding: [0x02,0xdc,0x00,0x31]
tgeu $20,$14,379 # CHECK: tgeu $20, $14, 379 # encoding: [0x02,0x8e,0x5e,0xf1]
tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} TLBP
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} TLBP_MM
tlbr # CHECK: tlbr # encoding: [0x42,0x00,0x00,0x01]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} TLBR
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} TLBR_MM
tlbwi # CHECK: tlbwi # encoding: [0x42,0x00,0x00,0x02]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} TLBWI
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} TLBWI_MM
tlbwr # CHECK: tlbwr # encoding: [0x42,0x00,0x00,0x06]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} TLBWR
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} TLBWR_MM
tlt $15,$13 # CHECK: tlt $15, $13 # encoding: [0x01,0xed,0x00,0x32]
tlt $2,$19,133 # CHECK: tlt $2, $19, 133 # encoding: [0x00,0x53,0x21,0x72]
tlti $14,-21059
Modified: llvm/trunk/test/MC/Mips/mips64r3/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64r3/valid.s?rev=329905&r1=329904&r2=329905&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64r3/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips64r3/valid.s Thu Apr 12 05:37:02 2018
@@ -1,6 +1,6 @@
# Instructions that are valid
#
-# RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64r3 | FileCheck %s
+# RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -show-inst -mcpu=mips64r3 | FileCheck %s
a:
.set noat
abs.d $f7,$f25 # CHECK: encoding:
@@ -261,6 +261,8 @@ a:
or $12,$s0,$sp
or $2, 4 # CHECK: ori $2, $2, 4 # encoding: [0x34,0x42,0x00,0x04]
pause # CHECK: pause # encoding: [0x00,0x00,0x01,0x40]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} PAUSE
+ # CHECK-NOT # <MCInst #{{[0-9}+}} PAUSE_MM
pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0xcc,0xa1,0x00,0x08]
# FIXME: Use the code generator in order to print the .set directives
# instead of the instruction printer.
@@ -285,7 +287,11 @@ a:
sc $15,18904($s3) # CHECK: sc $15, 18904($19) # encoding: [0xe2,0x6f,0x49,0xd8]
scd $15,-8243($sp) # CHECK: scd $15, -8243($sp) # encoding: [0xf3,0xaf,0xdf,0xcd]
sdbbp # CHECK: sdbbp # encoding: [0x70,0x00,0x00,0x3f]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SDBBP
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SDBBP_MM
sdbbp 34 # CHECK: sdbbp 34 # encoding: [0x70,0x00,0x08,0xbf]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SDBBP
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SDBBP_MM
sd $12,5835($10)
sdc1 $f31,30574($13)
sdc2 $20,23157($s2) # CHECK: sdc2 $20, 23157($18) # encoding: [0xfa,0x54,0x5a,0x75]
@@ -344,9 +350,17 @@ a:
tgeu $22,$28 # CHECK: tgeu $22, $gp # encoding: [0x02,0xdc,0x00,0x31]
tgeu $20,$14,379 # CHECK: tgeu $20, $14, 379 # encoding: [0x02,0x8e,0x5e,0xf1]
tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} TLBP
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} TLBP_MM
tlbr # CHECK: tlbr # encoding: [0x42,0x00,0x00,0x01]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} TLBR
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} TLBR_MM
tlbwi # CHECK: tlbwi # encoding: [0x42,0x00,0x00,0x02]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} TLBWI
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} TLBWI_MM
tlbwr # CHECK: tlbwr # encoding: [0x42,0x00,0x00,0x06]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} TLBWR
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} TLBWR_MM
tlt $15,$13 # CHECK: tlt $15, $13 # encoding: [0x01,0xed,0x00,0x32]
tlt $2,$19,133 # CHECK: tlt $2, $19, 133 # encoding: [0x00,0x53,0x21,0x72]
tlti $14,-21059
Modified: llvm/trunk/test/MC/Mips/mips64r5/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64r5/valid.s?rev=329905&r1=329904&r2=329905&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64r5/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips64r5/valid.s Thu Apr 12 05:37:02 2018
@@ -1,6 +1,6 @@
# Instructions that are valid
#
-# RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64r5 | FileCheck %s
+# RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -show-inst -mcpu=mips64r5 | FileCheck %s
a:
.set noat
abs.d $f7,$f25 # CHECK: encoding:
@@ -262,6 +262,8 @@ a:
or $12,$s0,$sp
or $2, 4 # CHECK: ori $2, $2, 4 # encoding: [0x34,0x42,0x00,0x04]
pause # CHECK: pause # encoding: [0x00,0x00,0x01,0x40]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} PAUSE
+ # CHECK-NOT # <MCInst #{{[0-9}+}} PAUSE_MM
pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0xcc,0xa1,0x00,0x08]
# FIXME: Use the code generator in order to print the .set directives
# instead of the instruction printer.
@@ -286,7 +288,11 @@ a:
sc $15,18904($s3) # CHECK: sc $15, 18904($19) # encoding: [0xe2,0x6f,0x49,0xd8]
scd $15,-8243($sp) # CHECK: scd $15, -8243($sp) # encoding: [0xf3,0xaf,0xdf,0xcd]
sdbbp # CHECK: sdbbp # encoding: [0x70,0x00,0x00,0x3f]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SDBBP
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SDBBP_MM
sdbbp 34 # CHECK: sdbbp 34 # encoding: [0x70,0x00,0x08,0xbf]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SDBBP
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SDBBP_MM
sd $12,5835($10)
sdc1 $f31,30574($13)
sdc2 $20,23157($s2) # CHECK: sdc2 $20, 23157($18) # encoding: [0xfa,0x54,0x5a,0x75]
@@ -352,9 +358,17 @@ a:
tgeu $22,$28 # CHECK: tgeu $22, $gp # encoding: [0x02,0xdc,0x00,0x31]
tgeu $20,$14,379 # CHECK: tgeu $20, $14, 379 # encoding: [0x02,0x8e,0x5e,0xf1]
tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} TLBP
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} TLBP_MM
tlbr # CHECK: tlbr # encoding: [0x42,0x00,0x00,0x01]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} TLBR
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} TLBR_MM
tlbwi # CHECK: tlbwi # encoding: [0x42,0x00,0x00,0x02]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} TLBWI
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} TLBWI_MM
tlbwr # CHECK: tlbwr # encoding: [0x42,0x00,0x00,0x06]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} TLBWR
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} TLBWR_MM
tlt $15,$13 # CHECK: tlt $15, $13 # encoding: [0x01,0xed,0x00,0x32]
tlt $2,$19,133 # CHECK: tlt $2, $19, 133 # encoding: [0x00,0x53,0x21,0x72]
tlti $14,-21059
Modified: llvm/trunk/test/MC/Mips/mips64r6/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64r6/valid.s?rev=329905&r1=329904&r2=329905&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64r6/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips64r6/valid.s Thu Apr 12 05:37:02 2018
@@ -10,7 +10,7 @@
# rs > rt
# appropriately for each branch instruction
#
-# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips64r6 2> %t0 | FileCheck %s
+# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -show-inst -mcpu=mips64r6 2> %t0 | FileCheck %s
# RUN: FileCheck %s -check-prefix=WARNING < %t0
a:
.set noat
@@ -204,6 +204,9 @@ a:
not $3, $4 # CHECK: not $3, $4 # encoding: [0x00,0x80,0x18,0x27]
not $3 # CHECK: not $3, $3 # encoding: [0x00,0x60,0x18,0x27]
or $2, 4 # CHECK: ori $2, $2, 4 # encoding: [0x34,0x42,0x00,0x04]
+ pause # CHECK: pause # encoding: [0x00,0x00,0x01,0x40]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} PAUSE
+ # CHECK-NOT # <MCInst #{{[0-9}+}} PAUSE_MM
pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0x7c,0xa1,0x04,0x35]
# FIXME: Use the code generator in order to print the .set directives
# instead of the instruction printer.
@@ -222,7 +225,11 @@ a:
sc $15,-40($s3) # CHECK: sc $15, -40($19) # encoding: [0x7e,0x6f,0xec,0x26]
scd $15,-51($sp) # CHECK: scd $15, -51($sp) # encoding: [0x7f,0xaf,0xe6,0xa7]
sdbbp # CHECK: sdbbp # encoding: [0x00,0x00,0x00,0x0e]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SDBBP
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SDBBP_MM
sdbbp 34 # CHECK: sdbbp 34 # encoding: [0x00,0x00,0x08,0x8e]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} SDBBP
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} SDBBP_MM
sdc2 $20,629($s2) # CHECK: sdc2 $20, 629($18) # encoding: [0x49,0xf4,0x92,0x75]
sel.d $f0,$f1,$f2 # CHECK: sel.d $f0, $f1, $f2 # encoding: [0x46,0x22,0x08,0x10]
sel.s $f0,$f1,$f2 # CHECK: sel.s $f0, $f1, $f2 # encoding: [0x46,0x02,0x08,0x10]
@@ -250,6 +257,18 @@ a:
sync 1 # CHECK: sync 1 # encoding: [0x00,0x00,0x00,0x4f]
syscall # CHECK: syscall # encoding: [0x00,0x00,0x00,0x0c]
syscall 256 # CHECK: syscall 256 # encoding: [0x00,0x00,0x40,0x0c]
+ tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} TLBP
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} TLBP_MM
+ tlbr # CHECK: tlbr # encoding: [0x42,0x00,0x00,0x01]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} TLBR
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} TLBR_MM
+ tlbwi # CHECK: tlbwi # encoding: [0x42,0x00,0x00,0x02]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} TLBWI
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} TLBWI_MM
+ tlbwr # CHECK: tlbwr # encoding: [0x42,0x00,0x00,0x06]
+ # CHECK-NEXT: # <MCInst #{{[0-9]+}} TLBWR
+ # CHECK-NOT: # <MCInst #{{[0-9]+}} TLBWR_MM
teq $0,$3 # CHECK: teq $zero, $3 # encoding: [0x00,0x03,0x00,0x34]
teq $5,$7,620 # CHECK: teq $5, $7, 620 # encoding: [0x00,0xa7,0x9b,0x34]
tge $5,$19,340 # CHECK: tge $5, $19, 340 # encoding: [0x00,0xb3,0x55,0x30]
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