[PATCH] D45230: [Power9]Legalize and emit code for converting (Un)Signed DWord to Quad-Precision

[Nemanja Ivanovic via Phabricator via llvm-commits]

nemanjai accepted this revision.
nemanjai added a comment.
This revision is now accepted and ready to land.

LGTM. Feel free to address the nit comments on the commit.



================
Comment at: lib/Target/PowerPC/PPCISelLowering.cpp:9413
+  case ISD::SINT_TO_FP:
+    // Legalize instruction for f128 result type
+    if (EnableQuadPrecision && (Op->getValueType(0) == MVT::f128))
----------------
Nit: complete sentences - don't forget the punctuation. Also, no need to be this generic here. Something like `// Conversions to f128 are legal.` should communicate this more clearly.


================
Comment at: test/CodeGen/PowerPC/f128-conv.ll:17
+; CHECK: mtvsrd [[REG:[0-9]+]], 4
+; CHECK-NEXT: xscvsdqp [[REG]], [[REG]]
+; CHECK-NEXT: stxv [[REG]], 0(3)
----------------
This isn't guaranteed to use the same register for input/output. Perhaps something like:
`; CHECK: xscvsdqp [[CONV:[0-9]+]], [[REG]]`
would be more appropriate (and of course, use `CONV` below).
This applies to all the tests below.


================
Comment at: test/CodeGen/PowerPC/f128-conv.ll:102
+; CHECK-NEXT: blr
+}
----------------
Please add a test case that will actually use the X-Form load. Perhaps something like:

```
void testXForm(__float128 *sink, signed char *a) {
  *sink = *((long long *) (a + 3));
}
```


https://reviews.llvm.org/D45230