[PATCH] D44905: [mips] Add support for Virtualization ASE

[Simon Dardis via Phabricator via llvm-commits]

sdardis added inline comments.


================
Comment at: lib/Target/Mips/MicroMipsInstrInfo.td:593
+  InstSE<(outs), (ins uimm10:$code_),
+          !strconcat(opstr, "\t$code_"), [], II_HYPCALL, FrmOther>;
+
----------------
This requires:

```
  let BaseOpcode = opstr;
```

like 'class LLEBaseMM'.


================
Comment at: lib/Target/Mips/MicroMipsInstrInfo.td:595
+
+class TLBINVMM<string opstr, InstrItinClass Itin> :
+  InstSE<(outs), (ins), opstr, [], Itin, FrmOther>;
----------------
As does this class.


================
Comment at: lib/Target/Mips/MicroMipsInstrInfo.td:1071-1084
+  def HYPCALL_MM  : HypcallMM<"hypcall">, POOL32A_HYPCALL_FM_MM,
+                    ISA_MICROMIPS32R5, ASE_VIRT;
+  def TLBGINV_MM  : TLBINVMM<"tlbginv", II_TLBGINV>,
+                    POOL32A_TLBINV_FM_MM<0x105>, ISA_MICROMIPS32R5, ASE_VIRT;
+  def TLBGINVF_MM : TLBINVMM<"tlbginvf", II_TLBGINVF>,
+                    POOL32A_TLBINV_FM_MM<0x145>, ISA_MICROMIPS32R5, ASE_VIRT;
+  def TLBGP_MM    : TLBINVMM<"tlbgp", II_TLBGP>,
----------------
All of these require MMRel.


================
Comment at: lib/Target/Mips/MipsInstrFormats.td:225
 //===----------------------------------------------------------------------===//
-class MFC3OP_FM<bits<6> op, bits<5> mfmt>
+class MFC3OP_FM<bits<6> op, bits<5> mfmt, bits<3> guest>
 {
----------------
This needs : StdArch


================
Comment at: lib/Target/Mips/MipsInstrInfo.td:2504
+class HYPCALL_FT<string opstr> :
+  InstSE<(outs), (ins uimm10:$code_),
+         !strconcat(opstr, "\t$code_"), [], II_HYPCALL, FrmOther, opstr>;
----------------
This requires:

let BaseOpcode = opstr;



================
Comment at: lib/Target/Mips/MipsInstrInfo.td:2508-2515
+  def MFGC0    : MFC3OP<"mfgc0", GPR32Opnd, COP0Opnd, II_MFGC0>,
+                 MFC3OP_FM<0x10, 3, 0>, ISA_MIPS32R5, ASE_VIRT;
+  def MTGC0    : MTC3OP<"mtgc0", COP0Opnd, GPR32Opnd, II_MTGC0>,
+                 MFC3OP_FM<0x10, 3, 2>, ISA_MIPS32R5, ASE_VIRT;
+  def MFHGC0   : MFC3OP<"mfhgc0", GPR32Opnd, COP0Opnd, II_MFHGC0>,
+                 MFC3OP_FM<0x10, 3, 4>, ISA_MIPS32R5, ASE_VIRT;
+  def MTHGC0   : MTC3OP<"mthgc0", COP0Opnd, GPR32Opnd, II_MTHGC0>,
----------------
These all need MMRel. You'll also need to modify the MFC3OP and MTC3OP classes to have 'let BaseName = opstr'.


================
Comment at: lib/Target/Mips/MipsInstrInfo.td:2528
+                 ISA_MIPS32R5, ASE_VIRT;
+  def HYPCALL  : MMRel, StdMMR6Rel, HYPCALL_FT<"hypcall">,
+                 HYPCALL_FM<0b101000>, ISA_MIPS32R5, ASE_VIRT;
----------------
This shouldn't be part of the StdMMR6Rel instruction mapping table, the MMRel table is enough.


================
Comment at: test/MC/Mips/virt/invalid.s:46-49
+  hypcall $4            # CHECK: :[[@LINE]]:11: error: expected 10-bit unsigned immediate
+  hypcall 2048          # CHECK: :[[@LINE]]:11: error: expected 10-bit unsigned immediate
+  hypcall -1            # CHECK: :[[@LINE]]:11: error: expected 10-bit unsigned immediate
+  hypcall 0($4)         # CHECK: :[[@LINE]]:12: error: unexpected token in argument list
----------------
You should reuse the same set of tests that you had for mthgc0 from lines 39-45. The check lines will differ obviously.


================
Comment at: test/MC/Mips/virt/invalid.s:50-61
+  tlbginv $2            # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
+  tlbginv 0             # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
+  tlbginvf $2           # CHECK: :[[@LINE]]:12: error: invalid operand for instruction
+  tlbginvf 0            # CHECK: :[[@LINE]]:12: error: invalid operand for instruction
+  tlbgp $2              # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
+  tlbgp 0               # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
+  tlbgr $2              # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
----------------
For each unique instruction here, you should reuse the same set of tests that you had for mthgc0 from lines 38-45. The check lines will differ obviously.


Repository:
  rL LLVM

https://reviews.llvm.org/D44905