[PATCH] D45560: [RISCV] Change function alignment to 4 bytes, and 2 bytes for RVC

[Kito Cheng via Phabricator via llvm-commits]

kito-cheng created this revision.
kito-cheng added reviewers: asb, apazos.
Herald added subscribers: llvm-commits, zzheng, shiva0217, niosHD, sabuasal, jordy.potman.lists, simoncook, johnrusso, rbar.

According RISC-V ELF psABI specification, base RV32 and RV64 ISAs only allow 32-bit instruction alignment, but allow to be aligned to 16-bit boundaries for C-extension.

So we just align to 4 bytes and 2 bytes for C-extension is enough.


Repository:
  rL LLVM

https://reviews.llvm.org/D45560

Files:
  lib/Target/RISCV/RISCVISelLowering.cpp


Index: lib/Target/RISCV/RISCVISelLowering.cpp
===================================================================
--- lib/Target/RISCV/RISCVISelLowering.cpp
+++ lib/Target/RISCV/RISCVISelLowering.cpp
@@ -142,8 +142,9 @@
   setBooleanContents(ZeroOrOneBooleanContent);
 
   // Function alignments (log2).
-  setMinFunctionAlignment(3);
-  setPrefFunctionAlignment(3);
+  unsigned FunctionAlignment = Subtarget.hasStdExtC() ? 1 : 2;
+  setMinFunctionAlignment(FunctionAlignment);
+  setPrefFunctionAlignment(FunctionAlignment);
 
   // Effectively disable jump table generation.
   setMinimumJumpTableEntries(INT_MAX);


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