[llvm] r329847 - [X86] Describe wbnoinvd instruction
Gabor Buella via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 11 13:01:57 PDT 2018
Author: gbuella
Date: Wed Apr 11 13:01:57 2018
New Revision: 329847
URL: http://llvm.org/viewvc/llvm-project?rev=329847&view=rev
Log:
[X86] Describe wbnoinvd instruction
Similar to the wbinvd instruction, except this
one does not invalidate caches. Ring 0 only.
The encoding matches a wbinvd instruction with
an F3 prefix.
Reviewers: craig.topper, zvi, ashlykov
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D43816
Added:
llvm/trunk/test/CodeGen/X86/wbnoinvd-intrinsic.ll
Modified:
llvm/trunk/include/llvm/IR/IntrinsicsX86.td
llvm/trunk/lib/Support/Host.cpp
llvm/trunk/lib/Target/X86/X86.td
llvm/trunk/lib/Target/X86/X86InstrInfo.td
llvm/trunk/lib/Target/X86/X86InstrSystem.td
llvm/trunk/lib/Target/X86/X86Subtarget.cpp
llvm/trunk/lib/Target/X86/X86Subtarget.h
llvm/trunk/test/MC/Disassembler/X86/x86-16.txt
llvm/trunk/test/MC/Disassembler/X86/x86-32.txt
llvm/trunk/test/MC/Disassembler/X86/x86-64.txt
llvm/trunk/test/MC/X86/x86-16.s
llvm/trunk/test/MC/X86/x86-32-coverage.s
llvm/trunk/test/MC/X86/x86-64.s
Modified: llvm/trunk/include/llvm/IR/IntrinsicsX86.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IR/IntrinsicsX86.td?rev=329847&r1=329846&r2=329847&view=diff
==============================================================================
--- llvm/trunk/include/llvm/IR/IntrinsicsX86.td (original)
+++ llvm/trunk/include/llvm/IR/IntrinsicsX86.td Wed Apr 11 13:01:57 2018
@@ -6401,3 +6401,12 @@ let TargetPrefix = "x86" in {
def int_x86_clzero : GCCBuiltin<"__builtin_ia32_clzero">,
Intrinsic<[], [llvm_ptr_ty], []>;
}
+
+//===----------------------------------------------------------------------===//
+// Cache line write back intrinsics
+
+// Write back no-invalidate
+let TargetPrefix = "x86" in {
+ def int_x86_wbnoinvd : GCCBuiltin<"__builtin_ia32_wbnoinvd">,
+ Intrinsic<[], [], []>;
+}
Modified: llvm/trunk/lib/Support/Host.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/Host.cpp?rev=329847&r1=329846&r2=329847&view=diff
==============================================================================
--- llvm/trunk/lib/Support/Host.cpp (original)
+++ llvm/trunk/lib/Support/Host.cpp Wed Apr 11 13:01:57 2018
@@ -1213,9 +1213,12 @@ bool sys::getHostCPUFeatures(StringMap<b
Features["tbm"] = HasExtLeaf1 && ((ECX >> 21) & 1);
Features["mwaitx"] = HasExtLeaf1 && ((ECX >> 29) & 1);
+ // Miscellaneous memory related features, detected by
+ // using the 0x80000008 leaf of the CPUID instruction
bool HasExtLeaf8 = MaxExtLevel >= 0x80000008 &&
!getX86CpuIDAndInfo(0x80000008, &EAX, &EBX, &ECX, &EDX);
- Features["clzero"] = HasExtLeaf8 && ((EBX >> 0) & 1);
+ Features["clzero"] = HasExtLeaf8 && ((EBX >> 0) & 1);
+ Features["wbnoinvd"] = HasExtLeaf8 && ((EBX >> 9) & 1);
bool HasLeaf7 =
MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX);
Modified: llvm/trunk/lib/Target/X86/X86.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86.td?rev=329847&r1=329846&r2=329847&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86.td (original)
+++ llvm/trunk/lib/Target/X86/X86.td Wed Apr 11 13:01:57 2018
@@ -249,6 +249,8 @@ def FeatureCLFLUSHOPT : SubtargetFeature
"Flush A Cache Line Optimized">;
def FeatureCLWB : SubtargetFeature<"clwb", "HasCLWB", "true",
"Cache Line Write Back">;
+def FeatureWBNOINVD : SubtargetFeature<"wbnoinvd", "HasWBNOINVD", "true",
+ "Write Back No Invalidate">;
def FeatureRDPID : SubtargetFeature<"rdpid", "HasRDPID", "true",
"Support RDPID instructions">;
// On some processors, instructions that implicitly take two memory operands are
@@ -825,6 +827,7 @@ def : IcelakeClientProc<"icelake-client"
class IcelakeServerProc<string Name> : ProcModel<Name, SkylakeServerModel,
ICLFeatures.Value, [
ProcIntelICX,
+ FeatureWBNOINVD,
FeatureHasFastGather
]>;
def : IcelakeServerProc<"icelake-server">;
Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=329847&r1=329846&r2=329847&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Wed Apr 11 13:01:57 2018
@@ -888,6 +888,7 @@ def HasSHSTK : Predicate<"Subtarget-
def HasIBT : Predicate<"Subtarget->hasIBT()">;
def HasCLFLUSHOPT : Predicate<"Subtarget->hasCLFLUSHOPT()">;
def HasCLWB : Predicate<"Subtarget->hasCLWB()">;
+def HasWBNOINVD : Predicate<"Subtarget->hasWBNOINVD()">;
def HasRDPID : Predicate<"Subtarget->hasRDPID()">;
def HasCmpxchg16b: Predicate<"Subtarget->hasCmpxchg16b()">;
def Not64BitMode : Predicate<"!Subtarget->is64Bit()">,
Modified: llvm/trunk/lib/Target/X86/X86InstrSystem.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSystem.td?rev=329847&r1=329846&r2=329847&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSystem.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSystem.td Wed Apr 11 13:01:57 2018
@@ -482,6 +482,12 @@ let Defs = [EAX, EBX, ECX, EDX], Uses =
let SchedRW = [WriteSystem] in {
def INVD : I<0x08, RawFrm, (outs), (ins), "invd", [], IIC_INVD>, TB;
def WBINVD : I<0x09, RawFrm, (outs), (ins), "wbinvd", [], IIC_INVD>, TB;
+
+// wbnoinvd is like wbinvd, except without invalidation
+// encoding: like wbinvd + an 0xF3 prefix
+def WBNOINVD : I<0x09, RawFrm, (outs), (ins), "wbnoinvd",
+ [(int_x86_wbnoinvd)], IIC_INVD>, XS,
+ Requires<[HasWBNOINVD]>;
} // SchedRW
//===----------------------------------------------------------------------===//
Modified: llvm/trunk/lib/Target/X86/X86Subtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.cpp?rev=329847&r1=329846&r2=329847&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86Subtarget.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86Subtarget.cpp Wed Apr 11 13:01:57 2018
@@ -324,6 +324,7 @@ void X86Subtarget::initializeEnvironment
HasSGX = false;
HasCLFLUSHOPT = false;
HasCLWB = false;
+ HasWBNOINVD = false;
HasRDPID = false;
UseRetpoline = false;
UseRetpolineExternalThunk = false;
Modified: llvm/trunk/lib/Target/X86/X86Subtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.h?rev=329847&r1=329846&r2=329847&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86Subtarget.h (original)
+++ llvm/trunk/lib/Target/X86/X86Subtarget.h Wed Apr 11 13:01:57 2018
@@ -360,6 +360,9 @@ protected:
/// Processor supports Cache Line Write Back instruction
bool HasCLWB;
+ /// Processor supports Write Back No Invalidate instruction
+ bool HasWBNOINVD;
+
/// Processor support RDPID instruction
bool HasRDPID;
@@ -621,6 +624,7 @@ public:
bool hasIBT() const { return HasIBT; }
bool hasCLFLUSHOPT() const { return HasCLFLUSHOPT; }
bool hasCLWB() const { return HasCLWB; }
+ bool hasWBNOINVD() const { return HasWBNOINVD; }
bool hasRDPID() const { return HasRDPID; }
bool useRetpoline() const { return UseRetpoline; }
bool useRetpolineExternalThunk() const { return UseRetpolineExternalThunk; }
Added: llvm/trunk/test/CodeGen/X86/wbnoinvd-intrinsic.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/wbnoinvd-intrinsic.ll?rev=329847&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/wbnoinvd-intrinsic.ll (added)
+++ llvm/trunk/test/CodeGen/X86/wbnoinvd-intrinsic.ll Wed Apr 11 13:01:57 2018
@@ -0,0 +1,18 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+wbnoinvd | FileCheck %s -check-prefix=CHECK32
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+wbnoinvd | FileCheck %s -check-prefix=CHECK64
+
+define void @wbnoinvd() nounwind {
+; CHECK32-LABEL: wbnoinvd:
+; CHECK32: # %bb.0:
+; CHECK32-NEXT: wbnoinvd
+; CHECK32-NEXT: retl
+;
+; CHECK64-LABEL: wbnoinvd:
+; CHECK64: # %bb.0:
+; CHECK64-NEXT: wbnoinvd
+; CHECK64-NEXT: retq
+ tail call void @llvm.x86.wbnoinvd()
+ ret void
+}
+declare void @llvm.x86.wbnoinvd() nounwind
Modified: llvm/trunk/test/MC/Disassembler/X86/x86-16.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/X86/x86-16.txt?rev=329847&r1=329846&r2=329847&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/X86/x86-16.txt (original)
+++ llvm/trunk/test/MC/Disassembler/X86/x86-16.txt Wed Apr 11 13:01:57 2018
@@ -791,3 +791,6 @@
# CHECK: callw -1
0xe8 0xff 0xff
+
+# CHECK: wbnoinvd
+0xf3 0x0f 0x09
Modified: llvm/trunk/test/MC/Disassembler/X86/x86-32.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/X86/x86-32.txt?rev=329847&r1=329846&r2=329847&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/X86/x86-32.txt (original)
+++ llvm/trunk/test/MC/Disassembler/X86/x86-32.txt Wed Apr 11 13:01:57 2018
@@ -820,3 +820,6 @@
# CHECK: ptwritel %eax
0xf3 0x0f 0xae 0xe0
+
+# CHECK: wbnoinvd
+0xf3 0x0f 0x09
Modified: llvm/trunk/test/MC/Disassembler/X86/x86-64.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/X86/x86-64.txt?rev=329847&r1=329846&r2=329847&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/X86/x86-64.txt (original)
+++ llvm/trunk/test/MC/Disassembler/X86/x86-64.txt Wed Apr 11 13:01:57 2018
@@ -516,3 +516,6 @@
# CHECK: ptwriteq %rax
0xf3 0x48 0x0f 0xae 0xe0
+
+# CHECK: wbnoinvd
+0xf3 0x0f 0x09
Modified: llvm/trunk/test/MC/X86/x86-16.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/x86-16.s?rev=329847&r1=329846&r2=329847&view=diff
==============================================================================
--- llvm/trunk/test/MC/X86/x86-16.s (original)
+++ llvm/trunk/test/MC/X86/x86-16.s Wed Apr 11 13:01:57 2018
@@ -969,3 +969,7 @@ data32
// CHECK: lgdtw 4(%eax)
// CHECK: encoding: [0x67,0x0f,0x01,0x50,0x04]
data32 lgdt 4(%eax)
+
+// CHECK: wbnoinvd
+// CHECK: encoding: [0xf3,0x0f,0x09]
+wbnoinvd
Modified: llvm/trunk/test/MC/X86/x86-32-coverage.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/x86-32-coverage.s?rev=329847&r1=329846&r2=329847&view=diff
==============================================================================
--- llvm/trunk/test/MC/X86/x86-32-coverage.s (original)
+++ llvm/trunk/test/MC/X86/x86-32-coverage.s Wed Apr 11 13:01:57 2018
@@ -2788,6 +2788,10 @@
// CHECK: encoding: [0x0f,0x09]
wbinvd
+// CHECK: wbnoinvd
+// CHECK: encoding: [0xf3,0x0f,0x09]
+ wbnoinvd
+
// CHECK: cpuid
// CHECK: encoding: [0x0f,0xa2]
cpuid
Modified: llvm/trunk/test/MC/X86/x86-64.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/x86-64.s?rev=329847&r1=329846&r2=329847&view=diff
==============================================================================
--- llvm/trunk/test/MC/X86/x86-64.s (original)
+++ llvm/trunk/test/MC/X86/x86-64.s Wed Apr 11 13:01:57 2018
@@ -1559,6 +1559,10 @@ ptwriteq 0xdeadbeef(%rbx,%rcx,8)
// CHECK: encoding: [0xf3,0x48,0x0f,0xae,0xe0]
ptwriteq %rax
+// CHECK: wbnoinvd
+// CHECK: encoding: [0xf3,0x0f,0x09]
+wbnoinvd
+
// __asm __volatile(
// "pushf \n\t"
// "popf \n\t"
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