[llvm] r329809 - [AArch64][AsmParser] Split index parsing from vector list.
Sander de Smalen via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 11 07:10:37 PDT 2018
Author: s.desmalen
Date: Wed Apr 11 07:10:37 2018
New Revision: 329809
URL: http://llvm.org/viewvc/llvm-project?rev=329809&view=rev
Log:
[AArch64][AsmParser] Split index parsing from vector list.
Summary:
Place parsing of a vector index into a separate function to reduce
duplication, since the code is duplicated in both the parsing of a
Neon vector register operand and a Neon vector list.
This is patch [2/6] in a series to add assembler/disassembler support for
SVE's contiguous ST1 (scalar+imm) instructions.
Reviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro
Reviewed By: rengolin
Subscribers: kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D45428
Modified:
llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
Modified: llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp?rev=329809&r1=329808&r2=329809&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp Wed Apr 11 07:10:37 2018
@@ -88,7 +88,7 @@ private:
int tryParseRegister();
bool parseRegister(OperandVector &Operands);
bool parseSymbolicImmVal(const MCExpr *&ImmVal);
- bool parseVectorList(OperandVector &Operands);
+ bool parseNeonVectorList(OperandVector &Operands);
bool parseOperand(OperandVector &Operands, bool isCondCode,
bool invertCondCode);
@@ -135,10 +135,12 @@ private:
OperandMatchResultTy tryParseAddSubImm(OperandVector &Operands);
OperandMatchResultTy tryParseGPR64sp0Operand(OperandVector &Operands);
bool tryParseNeonVectorRegister(OperandVector &Operands);
+ OperandMatchResultTy tryParseVectorIndex(OperandVector &Operands);
OperandMatchResultTy tryParseGPRSeqPair(OperandVector &Operands);
template <bool ParseSuffix>
OperandMatchResultTy tryParseSVEDataVector(OperandVector &Operands);
OperandMatchResultTy tryParseSVEPredicateVector(OperandVector &Operands);
+ bool tryParseVectorList(OperandVector &Operands);
OperandMatchResultTy tryParseSVEPattern(OperandVector &Operands);
public:
@@ -2676,28 +2678,33 @@ bool AArch64AsmParser::tryParseNeonVecto
Operands.push_back(
AArch64Operand::CreateToken(Kind, false, S, getContext()));
- // If there is an index specifier following the register, parse that too.
+ return tryParseVectorIndex(Operands) == MatchOperand_ParseFail;
+}
+
+OperandMatchResultTy
+AArch64AsmParser::tryParseVectorIndex(OperandVector &Operands) {
SMLoc SIdx = getLoc();
if (parseOptionalToken(AsmToken::LBrac)) {
const MCExpr *ImmVal;
if (getParser().parseExpression(ImmVal))
- return false;
+ return MatchOperand_NoMatch;
const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
if (!MCE) {
TokError("immediate value expected for vector index");
- return false;
+ return MatchOperand_ParseFail;;
}
SMLoc E = getLoc();
if (parseToken(AsmToken::RBrac, "']' expected"))
- return false;
+ return MatchOperand_ParseFail;;
Operands.push_back(AArch64Operand::CreateVectorIndex(MCE->getValue(), SIdx,
E, getContext()));
+ return MatchOperand_Success;
}
- return false;
+ return MatchOperand_NoMatch;
}
// tryParseVectorRegister - Try to parse a vector register name with
@@ -2876,8 +2883,8 @@ bool AArch64AsmParser::parseSymbolicImmV
return false;
}
-/// parseVectorList - Parse a vector list operand for AdvSIMD instructions.
-bool AArch64AsmParser::parseVectorList(OperandVector &Operands) {
+/// parseVectorList - Parse a vector list operand for vector instructions.
+bool AArch64AsmParser::tryParseVectorList(OperandVector &Operands) {
MCAsmParser &Parser = getParser();
assert(Parser.getTok().is(AsmToken::LCurly) && "Token is not a Left Bracket");
@@ -2961,26 +2968,15 @@ bool AArch64AsmParser::parseVectorList(O
Operands.push_back(AArch64Operand::CreateVectorList(
FirstReg, Count, NumElements, ElementWidth, S, getLoc(), getContext()));
- // If there is an index specifier following the list, parse that too.
- SMLoc SIdx = getLoc();
- if (parseOptionalToken(AsmToken::LBrac)) { // Eat left bracket token.
- const MCExpr *ImmVal;
- if (getParser().parseExpression(ImmVal))
- return false;
- const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
- if (!MCE) {
- TokError("immediate value expected for vector index");
- return false;
- }
+ return false;
+}
- SMLoc E = getLoc();
- if (parseToken(AsmToken::RBrac, "']' expected"))
- return false;
+/// parseNeonVectorList - Parse a vector list operand for AdvSIMD instructions.
+bool AArch64AsmParser::parseNeonVectorList(OperandVector &Operands) {
+ if (tryParseVectorList(Operands))
+ return true;
- Operands.push_back(AArch64Operand::CreateVectorIndex(MCE->getValue(), SIdx,
- E, getContext()));
- }
- return false;
+ return tryParseVectorIndex(Operands) == MatchOperand_ParseFail;
}
OperandMatchResultTy
@@ -3068,7 +3064,7 @@ bool AArch64AsmParser::parseOperand(Oper
return parseOperand(Operands, false, false);
}
case AsmToken::LCurly:
- return parseVectorList(Operands);
+ return parseNeonVectorList(Operands);
case AsmToken::Identifier: {
// If we're expecting a Condition Code operand, then just parse that.
if (isCondCode)
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