[llvm] r329802 - [X86][SSE] Tweak cmpps schedule test so that it works properly with just sse1

[Simon Pilgrim via llvm-commits]

Author: rksimon
Date: Wed Apr 11 06:15:36 2018
New Revision: 329802

URL: http://llvm.org/viewvc/llvm-project?rev=329802&view=rev
Log:
[X86][SSE] Tweak cmpps schedule test so that it works properly with just sse1

movhps/movlps test are still broken so we can't disable sse2 yet

Modified:
    llvm/trunk/test/CodeGen/X86/sse-schedule.ll

Modified: llvm/trunk/test/CodeGen/X86/sse-schedule.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse-schedule.ll?rev=329802&r1=329801&r2=329802&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/sse-schedule.ll (original)
+++ llvm/trunk/test/CodeGen/X86/sse-schedule.ll Wed Apr 11 06:15:36 2018
@@ -593,10 +593,11 @@ define <4 x float> @test_cmpps(<4 x floa
   %1 = fcmp oeq <4 x float> %a0, %a1
   %2 = load <4 x float>, <4 x float> *%a2, align 16
   %3 = fcmp oeq <4 x float> %a0, %2
-  %4 = or <4 x i1> %1, %3
-  %5 = sext <4 x i1> %4 to <4 x i32>
-  %6 = bitcast <4 x i32> %5 to <4 x float>
-  ret <4 x float> %6
+  %4 = sext <4 x i1> %1 to <4 x i32>
+  %5 = sext <4 x i1> %3 to <4 x i32>
+  %6 = or <4 x i32> %4, %5
+  %7 = bitcast <4 x i32> %6 to <4 x float>
+  ret <4 x float> %7
 }
 
 define float @test_cmpss(float %a0, float %a1, float *%a2) {