[PATCH] D45486: [X86][Atom] Convert Atom scheduler model to SchedRW (PR32431)

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon created this revision.
RKSimon added reviewers: craig.topper, andreadb, spatel, zvi, gadi.haber, delena, courbet.

Atom is the only x86 target that still uses schedule itineraries, if we can remove this then we can begin the work on removing x86 itineraries. I've also found that it will help with PR36550.

I've focussed on matching the existing model as closely as possible (relying on the schedule tests), PR36895 indicated a lot of these were incorrect but we can just as easily fix these after this patch as before. Hopefully we can get llvm-exegesis to help here,

This also required me to generalize the nop padding pass to work with TargetSchedModel instead of calling TargetInstrInfo::getInstrLatency directly - this could possibly be pre-committed if people are happy with it.

There are a few instructions that rely on itinerary scheduling (mainly push/pop/return) of multiple resource stages, but I don't think any of these are show stoppers.

There are also a few codegen changes that seem related to the post-ra scheduler acting a little differently, I haven't tracked these down but they don't seem critical.

NOTE: I don't have access to any Atom hardware, so this hasn't been tested in the wild.


Repository:
  rL LLVM

https://reviews.llvm.org/D45486

Files:
  lib/Target/X86/X86PadShortFunction.cpp
  lib/Target/X86/X86ScheduleAtom.td
  test/CodeGen/X86/lsr-loop-exit-cond.ll
  test/CodeGen/X86/lsr-static-addr.ll
  test/CodeGen/X86/mmx-schedule.ll
  test/CodeGen/X86/schedule-x86_32.ll
  test/CodeGen/X86/schedule-x86_64.ll
  test/CodeGen/X86/select.ll
  test/CodeGen/X86/sse-schedule.ll
  test/CodeGen/X86/sse2-schedule.ll
  test/CodeGen/X86/sse3-schedule.ll
  test/CodeGen/X86/ssse3-schedule.ll
  test/CodeGen/X86/x87-schedule.ll

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