[llvm] r329434 - [Hexagon] Handle subregisters when calculating iteration count in HW loops

[Krzysztof Parzyszek via llvm-commits]

Author: kparzysz
Date: Fri Apr  6 10:51:57 2018
New Revision: 329434

URL: http://llvm.org/viewvc/llvm-project?rev=329434&view=rev
Log:
[Hexagon] Handle subregisters when calculating iteration count in HW loops

Added:
    llvm/trunk/test/CodeGen/Hexagon/hwloop-subreg.ll
Modified:
    llvm/trunk/lib/Target/Hexagon/HexagonHardwareLoops.cpp

Modified: llvm/trunk/lib/Target/Hexagon/HexagonHardwareLoops.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonHardwareLoops.cpp?rev=329434&r1=329433&r2=329434&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonHardwareLoops.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonHardwareLoops.cpp Fri Apr  6 10:51:57 2018
@@ -928,6 +928,7 @@ CountValue *HexagonHardwareLoops::comput
       // 'Add' instruction.
       const MachineInstr *EndValInstr = MRI->getVRegDef(End->getReg());
       if (EndValInstr->getOpcode() == Hexagon::A2_addi &&
+          EndValInstr->getOperand(1).getSubReg() == 0 &&
           EndValInstr->getOperand(2).getImm() == StartV) {
         DistR = EndValInstr->getOperand(1).getReg();
       } else {

Added: llvm/trunk/test/CodeGen/Hexagon/hwloop-subreg.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/hwloop-subreg.ll?rev=329434&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/hwloop-subreg.ll (added)
+++ llvm/trunk/test/CodeGen/Hexagon/hwloop-subreg.ll Fri Apr  6 10:51:57 2018
@@ -0,0 +1,30 @@
+; RUN: llc -march=hexagon < %s
+; REQUIRES: asserts
+
+target triple = "hexagon"
+
+; Function Attrs: nounwind optsize readonly
+define void @f0() #0 align 2 {
+b0:
+  %v0 = load i32, i32* undef, align 8
+  %v1 = zext i32 %v0 to i64
+  %v2 = add nuw nsw i64 %v1, 63
+  %v3 = lshr i64 %v2, 6
+  %v4 = trunc i64 %v3 to i32
+  br i1 undef, label %b3, label %b1
+
+b1:                                               ; preds = %b0
+  %v5 = add nsw i32 %v4, -1
+  br label %b2
+
+b2:                                               ; preds = %b2, %b1
+  %v6 = phi i32 [ %v5, %b1 ], [ %v7, %b2 ]
+  %v7 = add i32 %v6, -1
+  %v8 = icmp sgt i32 %v7, -1
+  br i1 %v8, label %b2, label %b3
+
+b3:                                               ; preds = %b2, %b0
+  ret void
+}
+
+attributes #0 = { nounwind optsize readonly }