[llvm] r329404 - [ARC] Add <.f> suffix for F32_GEN4_{DOP|SOP}.

[Pete Couperus via llvm-commits]

Author: petecoup
Date: Fri Apr  6 08:43:11 2018
New Revision: 329404

URL: http://llvm.org/viewvc/llvm-project?rev=329404&view=rev
Log:
[ARC] Add <.f> suffix for F32_GEN4_{DOP|SOP}.

Add disassembler support for instructions which writeback STATUS32.
https://reviews.llvm.org/D45148

Patch by Yan Luo! (Yan.Luo2 at synopsys.com)


Modified:
    llvm/trunk/lib/Target/ARC/ARCInstrInfo.td
    llvm/trunk/test/MC/Disassembler/ARC/alu.txt

Modified: llvm/trunk/lib/Target/ARC/ARCInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARC/ARCInstrInfo.td?rev=329404&r1=329403&r2=329404&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARC/ARCInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARC/ARCInstrInfo.td Fri Apr  6 08:43:11 2018
@@ -125,18 +125,36 @@ multiclass ArcBinaryInst<bits<5> major,
                         (ins GPR32:$B, GPR32:$C),
                         !strconcat(opasm, "\t$A, $B, $C"),
                         []>;
+  def _f_rrr : F32_DOP_RR<major, mincode, 1, (outs GPR32:$A),
+                          (ins GPR32:$B, GPR32:$C),
+                          !strconcat(opasm, ".f\t$A, $B, $C"),
+                          []>
+  { let Defs = [STATUS32]; }
 
   // 2 register with unsigned 6-bit immediate variant.
   def _rru6 : F32_DOP_RU6<major, mincode, 0, (outs GPR32:$A),
                           (ins GPR32:$B, immU6:$U6),
                           !strconcat(opasm, "\t$A, $B, $U6"),
                           []>;
+  def _f_rru6 : F32_DOP_RU6<major, mincode, 1, (outs GPR32:$A),
+                            (ins GPR32:$B, immU6:$U6),
+                            !strconcat(opasm, ".f\t$A, $B, $U6"),
+                            []>
+  { let Defs = [STATUS32]; }
+
   // 2 register with 32-bit immediate variant.
   def _rrlimm : F32_DOP_RLIMM<major, mincode, 0,
-                      (outs GPR32:$A),
-                      (ins GPR32:$B, i32imm:$LImm),
-                      !strconcat(opasm, "\t$A, $B, $LImm"),
-                      []>;
+                              (outs GPR32:$A),
+                              (ins GPR32:$B, i32imm:$LImm),
+                              !strconcat(opasm, "\t$A, $B, $LImm"),
+                              []>;
+  def _f_rrlimm : F32_DOP_RLIMM<major, mincode, 1,
+                                (outs GPR32:$A),
+                                (ins GPR32:$B, i32imm:$LImm),
+                                !strconcat(opasm, ".f\t$A, $B, $LImm"),
+                                []>
+  { let Defs = [STATUS32]; }
+
   // 2 matched-register with signed 12-bit immediate variant (add r0, r0, -1).
   def _rrs12 : F32_DOP_RS12<major, mincode, 0,
                             (outs GPR32:$B),
@@ -144,6 +162,12 @@ multiclass ArcBinaryInst<bits<5> major,
                             !strconcat(opasm, "\t$B, $in, $S12"),
                             []>
   { let Constraints = "$B = $in"; }
+  def _f_rrs12 : F32_DOP_RS12<major, mincode, 1,
+                              (outs GPR32:$B),
+                              (ins GPR32:$in, immS<12>:$S12),
+                              !strconcat(opasm, ".f\t$B, $in, $S12"),
+                              []>
+  { let Constraints = "$B = $in"; let Defs = [STATUS32]; }
 }
 
 // Special multivariant GEN4 DOP format instruction that take 2 registers.
@@ -168,6 +192,10 @@ multiclass ArcUnaryInst<bits<5> major, b
                         string opasm> {
   def _rr : F32_SOP_RR<major, subop, 0, (outs GPR32:$B), (ins GPR32:$C),
                        !strconcat(opasm, "\t$B, $C"), []>;
+
+  def _f_rr : F32_SOP_RR<major, subop, 1, (outs GPR32:$B), (ins GPR32:$C),
+                       !strconcat(opasm, ".f\t$B, $C"), []>
+  { let Defs = [STATUS32]; }
 }
 
 

Modified: llvm/trunk/test/MC/Disassembler/ARC/alu.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARC/alu.txt?rev=329404&r1=329403&r2=329404&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARC/alu.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARC/alu.txt Fri Apr  6 08:43:11 2018
@@ -6,6 +6,9 @@
 # CHECK: add %r4, %r0, %r0 
 0x00 0x20 0x04 0x00 
 
+# CHECK: add.f %r4, %r0, %r0
+0x00 0x20 0x04 0x80
+
 # CHECK: add %r2, %r0, %r3 
 0x00 0x20 0xc2 0x00
 
@@ -18,21 +21,33 @@
 # CHECK: and %r2, %r7, %r4 
 0x04 0x27 0x02 0x01 
 
+# CHECK: and.f %r2, %r7, %r4
+0x04 0x27 0x02 0x81
+
 # CHECK: and %r2, %r7, 4 
 0x44 0x27 0x02 0x01 
 
 # CHECK: and %r1, %r1, 255
 0x84 0x21 0xc3 0x0f
 
+# CHECK: and.f %r1, %r1, 255
+0x84 0x21 0xc3 0x8f
+
 # CHECK: asl %r1, %r1, 2 
 0x40 0x29 0x81 0x00 
 
 # CHECK: asl %r0, %r0, %r0
 0x00 0x28 0x00 0x00
 
+# CHECK: asl.f %r0, %r0, %r0
+0x00 0x28 0x00 0x80
+
 # CHECK: asr %r1, %r2, 31
 0x42 0x2a 0xc1 0x07
 
+# CHECK: asr.f %r1, %r2, 31
+0x42 0x2a 0xc1 0x87
+
 # CHECK: asr %r1, %r3, 7
 0x42 0x2b 0xc1 0x01
 
@@ -54,6 +69,9 @@
 # CHECK: or %r18, %r16, 61440
 0x05 0x20 0x92 0x2f 0x00 0x00 0x00 0xf0
 
+# CHECK: or.f %r18, %r16, 61440
+0x05 0x20 0x92 0xaf 0x00 0x00 0x00 0xf0
+
 # CHECK: or %r1, %r1, %r14
 0x05 0x21 0x81 0x03
 
@@ -69,6 +87,9 @@
 # CHECK: sub %r2, %r7, %r4 
 0x02 0x27 0x02 0x01 
 
+# CHECK: sub.f %r2, %r7, %r4
+0x02 0x27 0x02 0x81
+
 # CHECK: sub %r0, %r22, %r0
 0x02 0x26 0x00 0x20
 
@@ -80,3 +101,6 @@
 
 # CHECK: sub3 %fp, %fp, -1
 0x99 0x23 0xff 0x3f
+
+# CHECK: sub3.f %fp, %fp, -1
+0x99 0x23 0xff 0xbf