[llvm] r329397 - [AMDGPU][MC][GFX9] Added s_dcache_discard* instructions
Dmitry Preobrazhensky via llvm-commits
llvm-commits at lists.llvm.org
Fri Apr 6 08:08:42 PDT 2018
Author: dpreobra
Date: Fri Apr 6 08:08:42 2018
New Revision: 329397
URL: http://llvm.org/viewvc/llvm-project?rev=329397&view=rev
Log:
[AMDGPU][MC][GFX9] Added s_dcache_discard* instructions
See bug 36838: https://bugs.llvm.org/show_bug.cgi?id=36838
Differential Revision: https://reviews.llvm.org/D45247
Reviewers: artem.tamazov, arsenm, timcorringham
Modified:
llvm/trunk/lib/Target/AMDGPU/SMInstructions.td
llvm/trunk/test/MC/AMDGPU/smem.s
llvm/trunk/test/MC/Disassembler/AMDGPU/smem_gfx9.txt
Modified: llvm/trunk/lib/Target/AMDGPU/SMInstructions.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SMInstructions.td?rev=329397&r1=329396&r2=329397&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SMInstructions.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/SMInstructions.td Fri Apr 6 08:08:42 2018
@@ -81,6 +81,18 @@ class SM_Store_Pseudo <string opName, da
let ScalarStore = 1;
}
+class SM_Discard_Pseudo <string opName, dag ins, bit isImm>
+ : SM_Pseudo<opName, (outs), ins, " $sbase, $offset"> {
+ let mayLoad = 0;
+ let mayStore = 0;
+ let has_glc = 0;
+ let has_sdst = 0;
+ let ScalarStore = 0;
+ let hasSideEffects = 1;
+ let offset_is_imm = isImm;
+ let PseudoInstr = opName # !if(isImm, "_IMM", "_SGPR");
+}
+
multiclass SM_Pseudo_Loads<string opName,
RegisterClass baseClass,
RegisterClass dstClass> {
@@ -125,6 +137,11 @@ multiclass SM_Pseudo_Stores<string opNam
}
}
+multiclass SM_Pseudo_Discards<string opName> {
+ def _IMM : SM_Discard_Pseudo <opName, (ins SReg_64:$sbase, smrd_offset_20:$offset), 1>;
+ def _SGPR : SM_Discard_Pseudo <opName, (ins SReg_64:$sbase, SReg_32:$offset), 0>;
+}
+
class SM_Time_Pseudo<string opName, SDPatternOperator node> : SM_Pseudo<
opName, (outs SReg_64_XEXEC:$sdst), (ins),
" $sdst", [(set i64:$sdst, (node))]> {
@@ -332,6 +349,11 @@ defm S_ATOMIC_DEC_X2 : SM_P
} // let SubtargetPredicate = HasScalarAtomics
+let SubtargetPredicate = isGFX9 in {
+defm S_DCACHE_DISCARD : SM_Pseudo_Discards <"s_dcache_discard">;
+defm S_DCACHE_DISCARD_X2 : SM_Pseudo_Discards <"s_dcache_discard_x2">;
+}
+
//===----------------------------------------------------------------------===//
// Scalar Memory Patterns
//===----------------------------------------------------------------------===//
@@ -636,6 +658,14 @@ defm S_ATOMIC_XOR_X2 : SM_R
defm S_ATOMIC_INC_X2 : SM_Real_Atomics_vi <0xab, "S_ATOMIC_INC_X2">;
defm S_ATOMIC_DEC_X2 : SM_Real_Atomics_vi <0xac, "S_ATOMIC_DEC_X2">;
+multiclass SM_Real_Discard_vi<bits<8> op, string ps> {
+ def _IMM_vi : SMEM_Real_vi <op, !cast<SM_Discard_Pseudo>(ps#_IMM)>;
+ def _SGPR_vi : SMEM_Real_vi <op, !cast<SM_Discard_Pseudo>(ps#_SGPR)>;
+}
+
+defm S_DCACHE_DISCARD : SM_Real_Discard_vi <0x28, "S_DCACHE_DISCARD">;
+defm S_DCACHE_DISCARD_X2 : SM_Real_Discard_vi <0x29, "S_DCACHE_DISCARD_X2">;
+
//===----------------------------------------------------------------------===//
// CI
//===----------------------------------------------------------------------===//
Modified: llvm/trunk/test/MC/AMDGPU/smem.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AMDGPU/smem.s?rev=329397&r1=329396&r2=329397&view=diff
==============================================================================
--- llvm/trunk/test/MC/AMDGPU/smem.s (original)
+++ llvm/trunk/test/MC/AMDGPU/smem.s Fri Apr 6 08:08:42 2018
@@ -214,6 +214,26 @@ s_scratch_store_dwordx4 s[4:7], s[4:5],
// NOSICIVI: error
//===----------------------------------------------------------------------===//
+// s_dcache_discard instructions
+//===----------------------------------------------------------------------===//
+
+s_dcache_discard s[2:3], s0
+// GFX9: s_dcache_discard s[2:3], s0 ; encoding: [0x01,0x00,0xa0,0xc0,0x00,0x00,0x00,0x00]
+// NOSICIVI: error: instruction not supported on this GPU
+
+s_dcache_discard s[2:3], 0x0
+// GFX9: s_dcache_discard s[2:3], 0x0 ; encoding: [0x01,0x00,0xa2,0xc0,0x00,0x00,0x00,0x00]
+// NOSICIVI: error: instruction not supported on this GPU
+
+s_dcache_discard_x2 s[2:3], s101
+// GFX9: s_dcache_discard_x2 s[2:3], s101 ; encoding: [0x01,0x00,0xa4,0xc0,0x65,0x00,0x00,0x00]
+// NOSICIVI: error: instruction not supported on this GPU
+
+s_dcache_discard_x2 s[2:3], 0x0
+// GFX9: s_dcache_discard_x2 s[2:3], 0x0 ; encoding: [0x01,0x00,0xa6,0xc0,0x00,0x00,0x00,0x00]
+// NOSICIVI: error: instruction not supported on this GPU
+
+//===----------------------------------------------------------------------===//
// s_atomic instructions
//===----------------------------------------------------------------------===//
Modified: llvm/trunk/test/MC/Disassembler/AMDGPU/smem_gfx9.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/AMDGPU/smem_gfx9.txt?rev=329397&r1=329396&r2=329397&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/AMDGPU/smem_gfx9.txt (original)
+++ llvm/trunk/test/MC/Disassembler/AMDGPU/smem_gfx9.txt Fri Apr 6 08:08:42 2018
@@ -32,6 +32,22 @@
0x02,0x01,0x5d,0xc0,0x00,0x00,0x00,0x00
#===------------------------------------------------------------------------===#
+# s_dcache_discard
+#===------------------------------------------------------------------------===#
+
+# GFX9: s_dcache_discard s[100:101], s0 ; encoding: [0x32,0x00,0xa0,0xc0,0x00,0x00,0x00,0x00]
+0x32,0x00,0xa0,0xc0,0x00,0x00,0x00,0x00
+
+# GFX9: s_dcache_discard s[2:3], 0x0 ; encoding: [0x01,0x00,0xa2,0xc0,0x00,0x00,0x00,0x00]
+0x01,0x00,0xa2,0xc0,0x00,0x00,0x00,0x00
+
+# GFX9: s_dcache_discard_x2 s[2:3], s101 ; encoding: [0x01,0x00,0xa4,0xc0,0x65,0x00,0x00,0x00]
+0x01,0x00,0xa4,0xc0,0x65,0x00,0x00,0x00
+
+# GFX9: s_dcache_discard_x2 s[2:3], 0x0 ; encoding: [0x01,0x00,0xa6,0xc0,0x00,0x00,0x00,0x00]
+0x01,0x00,0xa6,0xc0,0x00,0x00,0x00,0x00
+
+#===------------------------------------------------------------------------===#
# s_atomic
#===------------------------------------------------------------------------===#
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