[llvm] r329389 - [X86][SandyBridge] Add (V)DPPS memory fold latencies
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Fri Apr 6 04:25:21 PDT 2018
Author: rksimon
Date: Fri Apr 6 04:25:21 2018
New Revision: 329389
URL: http://llvm.org/viewvc/llvm-project?rev=329389&view=rev
Log:
[X86][SandyBridge] Add (V)DPPS memory fold latencies
Noticed this during D44654
Modified:
llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td
llvm/trunk/test/CodeGen/X86/avx-schedule.ll
llvm/trunk/test/CodeGen/X86/sse41-schedule.ll
Modified: llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td?rev=329389&r1=329388&r2=329389&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td Fri Apr 6 04:25:21 2018
@@ -1954,6 +1954,20 @@ def SBWriteResGroup120 : SchedWriteRes<[
}
def: InstRW<[SBWriteResGroup120], (instregex "(V?)DPPDrmi")>;
+def SBWriteResGroup121 : SchedWriteRes<[SBPort0,SBPort1,SBPort5,SBPort23]> {
+ let Latency = 18;
+ let NumMicroOps = 5;
+ let ResourceCycles = [1,2,1,1];
+}
+def: InstRW<[SBWriteResGroup121], (instregex "(V?)DPPSrmi")>;
+
+def SBWriteResGroup122 : SchedWriteRes<[SBPort0,SBPort1,SBPort5,SBPort23]> {
+ let Latency = 19;
+ let NumMicroOps = 5;
+ let ResourceCycles = [1,2,1,1];
+}
+def: InstRW<[SBWriteResGroup122], (instregex "VDPPSYrmi")>;
+
def SBWriteResGroup123 : SchedWriteRes<[SBPort0,SBPort23,SBFPDivider]> {
let Latency = 20;
let NumMicroOps = 2;
Modified: llvm/trunk/test/CodeGen/X86/avx-schedule.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-schedule.ll?rev=329389&r1=329388&r2=329389&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx-schedule.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx-schedule.ll Fri Apr 6 04:25:21 2018
@@ -1607,13 +1607,13 @@ define <8 x float> @test_dpps(<8 x float
; GENERIC-LABEL: test_dpps:
; GENERIC: # %bb.0:
; GENERIC-NEXT: vdpps $7, %ymm1, %ymm0, %ymm0 # sched: [12:2.00]
-; GENERIC-NEXT: vdpps $7, (%rdi), %ymm0, %ymm0 # sched: [8:1.00]
+; GENERIC-NEXT: vdpps $7, (%rdi), %ymm0, %ymm0 # sched: [19:2.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SANDY-LABEL: test_dpps:
; SANDY: # %bb.0:
; SANDY-NEXT: vdpps $7, %ymm1, %ymm0, %ymm0 # sched: [12:2.00]
-; SANDY-NEXT: vdpps $7, (%rdi), %ymm0, %ymm0 # sched: [8:1.00]
+; SANDY-NEXT: vdpps $7, (%rdi), %ymm0, %ymm0 # sched: [19:2.00]
; SANDY-NEXT: retq # sched: [1:1.00]
;
; HASWELL-LABEL: test_dpps:
Modified: llvm/trunk/test/CodeGen/X86/sse41-schedule.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse41-schedule.ll?rev=329389&r1=329388&r2=329389&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/sse41-schedule.ll (original)
+++ llvm/trunk/test/CodeGen/X86/sse41-schedule.ll Fri Apr 6 04:25:21 2018
@@ -623,7 +623,7 @@ define <4 x float> @test_dpps(<4 x float
; GENERIC-LABEL: test_dpps:
; GENERIC: # %bb.0:
; GENERIC-NEXT: dpps $7, %xmm1, %xmm0 # sched: [12:2.00]
-; GENERIC-NEXT: dpps $7, (%rdi), %xmm0 # sched: [8:1.00]
+; GENERIC-NEXT: dpps $7, (%rdi), %xmm0 # sched: [18:2.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SLM-LABEL: test_dpps:
@@ -635,13 +635,13 @@ define <4 x float> @test_dpps(<4 x float
; SANDY-SSE-LABEL: test_dpps:
; SANDY-SSE: # %bb.0:
; SANDY-SSE-NEXT: dpps $7, %xmm1, %xmm0 # sched: [12:2.00]
-; SANDY-SSE-NEXT: dpps $7, (%rdi), %xmm0 # sched: [8:1.00]
+; SANDY-SSE-NEXT: dpps $7, (%rdi), %xmm0 # sched: [18:2.00]
; SANDY-SSE-NEXT: retq # sched: [1:1.00]
;
; SANDY-LABEL: test_dpps:
; SANDY: # %bb.0:
; SANDY-NEXT: vdpps $7, %xmm1, %xmm0, %xmm0 # sched: [12:2.00]
-; SANDY-NEXT: vdpps $7, (%rdi), %xmm0, %xmm0 # sched: [8:1.00]
+; SANDY-NEXT: vdpps $7, (%rdi), %xmm0, %xmm0 # sched: [18:2.00]
; SANDY-NEXT: retq # sched: [1:1.00]
;
; HASWELL-SSE-LABEL: test_dpps:
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