[PATCH] D45351: [X86] Attempt to model basic arithmetic instructions in the Haswell/Broadwell/Skylake scheduler models without InstRWs

[Andrea Di Biagio via Phabricator via llvm-commits]

andreadb accepted this revision.
andreadb added a comment.
This revision is now accepted and ready to land.

Nice cleanup!

LGTM.



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Comment at: lib/Target/X86/X86InstrArithmetic.td:855-856
                                    typeinfo.RegClass:$src))]>,
-            Sched<[WriteALULd, ReadAfterLd]>;
+            Sched<[WriteALULd, ReadDefault, ReadDefault, ReadDefault,
+                   ReadDefault, ReadDefault, ReadAfterLd]>;
 
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It is a shame that we cannot concatenate lists in tablegen. If we had the concept of read sequence (and concatenation), we could have avoided to have to repeat ReadDefault for five times.


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Comment at: lib/Target/X86/X86InstrArithmetic.td:924
                                     typeinfo.Imm8Operator:$src))]>,
-             Sched<[WriteALULd, ReadAfterLd]>;
 
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Nice catch.


https://reviews.llvm.org/D45351