[PATCH] D45355: [SelectionDAG] Fix return calling convention in expansion of ?MULO

[whitequark via Phabricator via llvm-commits]

whitequark created this revision.
whitequark added reviewers: eli.friedman, vadimcn.

The SMULO/UMULO DAG nodes, when not directly supported by the target,
expand to a multiplication twice as wide. In case that the resulting
type is not legal, the legalizer cannot directly call the intrinsic with
the wide arguments; instead, it "pre-lowers" them by splitting them
in halves.

https://reviews.llvm.org/rL283203 made sure that on big endian targets, the legalizer passes
the argument halves in the correct order. It did not do the same
for the return value halves because the existing code used a hack;
it put an illegal type into DAG and hoped that nothing would break
and it would be correctly lowered elsewhere.

https://reviews.llvm.org/rL307207 fixed this, handling return value halves similar to how
argument handles are handled, but did not take big-endian targets
into account.

This commit fixes the expansion on big-endian targets, such as
the out-of-tree OR1K target.


Repository:
  rL LLVM

https://reviews.llvm.org/D45355

Files:
  lib/CodeGen/SelectionDAG/LegalizeDAG.cpp


Index: lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -3619,8 +3619,14 @@
       }
       assert(Ret.getOpcode() == ISD::MERGE_VALUES &&
              "Ret value is a collection of constituent nodes holding result.");
-      BottomHalf = Ret.getOperand(0);
-      TopHalf = Ret.getOperand(1);
+      if(DAG.getDataLayout().isLittleEndian()) {
+        // Same as above.
+        BottomHalf = Ret.getOperand(0);
+        TopHalf = Ret.getOperand(1);
+      } else {
+        BottomHalf = Ret.getOperand(1);
+        TopHalf = Ret.getOperand(04);
+      }
     }
 
     if (isSigned) {


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